Signal generation circuit, jitter injection circuit, semiconductor chip and test apparatus

A test apparatus for testing a device under test, the test apparatus comprising:

• a pattern generating section that generates a predetermined logic pattern;
• a signal generation circuit that generates a clock signal including jitter injected thereto;
• a waveform shaping section that generates a test signal by sampling the logic pattern in accordance with the clock signal, and inputs the generated test signal into the device under test;
• and
• a judging section that judges acceptability of the device under test based on a to-be-measured signal output from the device under test in response to the test signal, wherein
• the signal generation circuit includes:
• a jitter output section that outputs a first jitter signal and a second jitter signal which have different frequencies from each other;
• a carrier output section that outputs a caner signal having a frequency positioned in substantially the middle between the frequencies of the first and second jitter signals;
• and
• an adding section that adds together the first jitter signal, second jitter signal and carrier signal so as to generate the output signal.