System and method for balancing cells in a battery pack with selective bypass paths

A cell balancing circuit comprising:

• a plurality of cells of a battery pack;
• an internal bypass path for each cell of said plurality of cells;
• an external bypass path for each cell of said plurality of cells;
• an input for receiving an enable signal for each cell of said plurality of cells, wherein said enable signal is configured to enable a bypass current of each cell of said plurality of cells;
• a current source for each cell of said plurality of cells configured to provide a variable bias current, wherein said bias current selects among a combination of said internal bypass path and said external bypass path for each cell of said plurality of cells;
• and
• a driving circuit for receiving said enable signal and said bias current for each cell of said plurality of cells, and for providing a configuration signal for each cell of said plurality of cells configured to selectively conduct among said combination for each cell of said plurality of cells.

A method for balancing a battery pack comprising:

• receiving an enable signal for each cell of a plurality of cells for enabling a bypass current of each cell of said plurality of cells;
• receiving a selection signal for each cell of said plurality of cells for selecting among a combination of an internal bypass path and an external bypass path for each cell of said plurality of cells;
• generating a configuration signal for each cell of said plurality of cells for selectively conducting among said combination for each cell of said plurality of cells;
• and
• conducting among said combination for each cell of said plurality of cells.

An electronic device comprising:

• a plurality of cells of a battery pack;
• a monitoring circuit for monitoring a voltage level of each cell of said plurality of cells and providing a monitoring signal for each cell of said plurality of cells representative of each said voltage level;
• a processor for receiving each said monitoring signal, and providing an enable signal and a selection signal for each cell of said plurality of cells, wherein said enable signal representative of said voltage level of each cell of said plurality of cells greater than a first predetermined threshold or a voltage difference between said voltage level and a minimum of said voltage level greater than a second predetermined threshold;
• and
• a cell balancing circuit for receiving each said enable signal and said selection signal, and balancing said plurality of cells, said cell balancing circuit comprising:
• an internal bypass path for each cell of said plurality of cells;
• an external bypass path for each cell of said plurality of cells;
• a first input for receiving said enable signal from said processor for conducting bypass current for each cell of said plurality of cells;
• a second input for receiving said selection signal from said processor for selecting among a combination of said internal bypass path and said external bypass path for each cell of said plurality of cells;
• and
• a driving circuit for receiving said enable signal and said selection signal and for providing a configuration signal configured to selectively conduct among said combination of for each cell of said plurality of cells.