Interconnect structures with surfaces roughness improving liner and methods for fabricating the same

A semiconductor structure, comprising:

• a dual damascene structure, comprising:
• a substrate with a low-k dielectric layer thereon;
• a via opening and a trench opening formed in the low-k dielectric layer, wherein the trench opening is formed over the via opening and the via opening exposes a portion of the substrate;
• a liner layer formed on sidewalls of the low-k dielectric layer exposed by the trench and via portions and a bottom surface exposed by the trench via portion, wherein the portion of the liner layer on sidewalls of the low-k dielectric layer exposed by the trench and via portions and the portion of the liner layer formed on a bottom surface exposed by the trench portion comprise different materials;
• a conformal conductive barrier layer formed in the trench and via openings, covering the liner layer and the exposed portion of the substrate;
• and
• a conductive layer formed on the conductive barrier layer, filling in the trench and via openings;
• and
• a passivation layer formed over the dual damascene structure.

An interconnect structure, comprising:

• a substrate with a low-k dielectric layer thereon;
• a via opening and a trench opening formed in the low-k dielectric layer, wherein the trench opening is formed over the via opening and the via opening exposes a portion of the substrate;
• and
• a liner layer formed on sidewalls of the low-k dielectric layer exposed by the trench and via portions and a bottom surface exposed by the trench via portion, wherein the portion of the liner layer on sidewalls of the low-k dielectric layer exposed by the trench and via portions and the portion of the liner layer formed on a bottom surface exposed by the trench portion comprise different materials.