Back to results
US 7,466,021 B2Granted
Memory packages having stair step interconnection layers
AssigneeInterconnect Portfolio LLC
InventorJoseph Charles Fjelstad
Life of this patent
Estimating the term…
Abstract
Disclosed are IC package structures having stair stepped layers and which have no plated vias. Such structures can be fabricated either as discrete packages or as strips such as might be beneficial in for use with memory devices wherein critical or high speed signals can be routed along the length of the multi-chip strip package without having to have the signals ascend and descend from the interconnection substrate on which the assembly is mounted to the IC package termination and back as the signal transmits between devices.
Claims10
An IC package assembly comprising:
- first and second IC die, each die having an interface surface;
- a first array of IC terminal contacts disposed on the interface surface of the first IC die;
- a second array of IC terminal contacts disposed on the interface surface of the second IC die;
- a first electrically insulating layer with first and second surfaces and a first edge, the first surface of being coupled to the interface surfaces of the first and second IC die, and the first edge having conductive IO terminations configured to electrically couple with an edge connector;
- first and second apertures within the first insulating layer, the first aperture having a first periphery circumscribing at least part of the first array of terminals, and the second aperture having a second periphery circumscribing at least part of the second array of terminals;
- conductive pathways disposed on the second surface, including at first conductive pathway terminating proximate the first periphery and a second conductive pathway terminating proximate the second periphery;
- a first wire bond coupling the first conductive pathway to an IC terminal within the first aperture and a second wire bond coupling the second conductive pathway to an IC terminal within the second aperture;
- a second electrically insulating layer having first and second surfaces, wherein the first surface of the second insulating layer coupled to the second surface of the first insulating layer;
- conductive circuits disposed on the second surface of the second insulating layer;
- a third aperture in the second insulating layer having a third periphery that circumscribes at least part of the first array of IC terminals, and wherein the third periphery circumscribes an area on the second surface of the first insulating layer, including a portion of the first conductive pathway;
- a fourth aperture in the second insulating layer having a fourth periphery that circumscribes at least part of the second array of IC terminals, and circumscribes an area on the second surface of the first insulating layer including a portion of the second conductive pathway.
8 more elements
Dependencies are inferred from the claim text.