Method for reducing dislocation threading using a suppression implant

A semiconductor device, comprising:

• a doped well located within a substrate;
• one or more active junctions located within the doped well;
• and
• a suppression implant located within the doped well, wherein a peak concentration of the suppression implant is located between a peak concentration of the p-type well and a lowest portion of the one or more active junctions.

A voltage protection circuit, comprising:

• an input pad;
• one or more zener diodes electrically coupled to the input pad, the one or more zener diodes configured to clamp the input voltage, each of the one or more zener diodes comprising:
• a p-type well located within a substrate;
• a cathode and an anode located within the p-type well;
• and
• a suppression implant located within the substrate proximate the p-type well and configured to reduce threading dislocations;
• and
• a circuit for receiving the input voltage or the clamped input voltage.