Low tunnel barrier insulators

A programmable logic array, comprising:

• a plurality of input lines for receiving an input signal;
• a plurality of output lines;
• and
• one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to a received input signal, wherein the plurality of logic cells includes a logic cell comprising:
• a first source/drain region formed on a substrate;
• a body region including a channel region formed on the first source/drain region;
• a second source/drain region formed on the body region;
• a floating gate opposing the channel region and separated therefrom by a gate oxide;
• a control gate opposing the floating gate;
• and
• wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator having a tunneling barrier of less than 2.0 eV, and having a number of small compositional ranges such that gradients can be formed by an applied electric field which produce different barrier heights at an interface with the floating gate and control gate.

An electronic system, comprising:

• a processor;
• and
• a memory device coupled to the processor, wherein at least one of the memory device and the processor includes an array of flash memory cells, comprising:
• a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region;
• a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide;
• a number of control gates opposing the floating gates;
• a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells;
• a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of flash memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator having a tunneling barrier of less than 2.0 eV, and having a number of small compositional ranges such that gradients can be formed by an applied electric field which produce different barrier heights at an interface with the floating gate and control gate;
• and
• a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of flash cells.