Method for fabricating semiconductor device to lower source/drain sheet resistance

A method for fabricating a semiconductor device to lower source/drain sheet resistance, comprising:

• providing a semiconductor device with at least one gate region and two junction regions;
• depositing a silicon layer or SiGe epitaxial layer on the gate region and the two junction regions;
• forming a dielectric layer on the semiconductor device, wherein the dielectric layer is provided with a plurality of contact windows corresponding to the gate region and the two junction regions, so as to expose a part of the silicon layer or SiGe epitaxial layer ob the gate region and the two junction regions;
• depositing a metal layer to cover the exposed silicon layer or the exposed SiGe epitaxial layer in the contact windows and the rest of the dielectric layer;
• and
• conducting a heat treatment of the semiconductor device in a nitrogen-containing environment, such that the silicon layer or the SiGe epitaxial layer and the metal layer are reacted, so as to convert the silicon layer or the SiGe epitaxial layer into a silicide.