Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures

A method for fabricating a chip-on-glass assembly for an LCD driver IC die, comprising:

• sputtering a titanium-containing layer over a semiconductor substrate, wherein said titanium-containing layer has a thickness between 1,000 and 10,000 Angstroms;
• sputtering a first gold layer over said semiconductor substrate and on said titanium- containing layer;
• depositing a first photoresist layer on said first gold layer, wherein an opening in said first photoresist layer is over said first gold layer and exposes said first gold layer;
• electroplating a second gold layer on said first gold layer exposed by said opening in said first photoresist layer, wherein said second gold layer has a thickness between 2 and 30 micrometers;
• removing said first photoresist layer;
• depositing a second photoresist layer over said first and second gold layers, wherein an opening in said second photoresist layer is over said second gold layer and exposes said second gold layer;
• electroplating a gold bump directly on said second gold layer exposed by said opening in said second photoresist layer, wherein said gold bump has a thickness between 7 and 100 micrometers;
• after said electroplating said gold bump, removing said second photoresist layer;
• after said removing said second photoresist layer, removing said titanium-containing layer and said first gold layer not under said second gold layer;
• and
• connecting said gold bump to a glass substrate.

A method for fabricating a chip-on-glass assembly for an LCD driver IC die, comprising:

• providing a wafer with a semiconductor substrate, a transistor in and on said semiconductor substrate, a first metal layer over said semiconductor substrate, a second metal layer over said semiconductor substrate and over said first metal layer, a dielectric layer between said first and second metal layers, a passivation layer over said semiconductor substrate, over said first and second metal layers and over said dielectric layer, wherein said passivation layer comprises a nitride layer having a thickness between 0.2 and 1.2 micrometers, and a contact pad over said semiconductor substrate, wherein said contact pad is exposed by an opening in said passivation layer;
• sputtering an adhesion/barrier layer over said wafer;
• sputtering a first metal layer over said adhesion/barrier layer;
• depositing a first photoresist layer on said first metal layer, wherein an opening in said first photoresist layer is over said first metal layer and exposes said first metal layer;
• electroplating a second metal layer directly on said first metal layer exposed by said opening in said first photoresist layer, wherein said second metal layer has a thickness between 2 and 30 micrometers;
• removing said first photoresist layer;
• depositing a second photoresist layer over said first and second metal layers, wherein an opening in said second photoresist layer is over said second metal layer and exposes said second metal layer;
• forming a gold layer over said second metal layer under said opening in said second photoresist layer;
• after said forming said gold layer, removing said second photoresist layer;
• after said removing said second photoresist layer, removing said adhesion/barrier layer and said first metal layer not under said second metal layer;
• and
• connecting said gold layer to a glass substrate.