Reliable metal bumps on top of I/O pads after removal of test probe marks

A wafer comprising:

• a silicon substrate;
• a dielectric layer over said silicon substrate;
• a metal pad on said dielectric layer, wherein a first opening completely through said metal pad is over said dielectric layer, and said dielectric layer has a region at a bottom of said first opening;
• a passivation layer on said metal pad and over said dielectric layer, wherein a second opening in said passivation layer is over said first opening and over said region;
• and
• a copper layer over region said wherein said copper layer is connected to said metal pad through said second opening.

A wafer comprising:

• a silicon substrate;
• a dielectric layer over said silicon substrate;
• a via in said dielectric layer, wherein said via penetrates through said dielectric layer;
• a metal pad on said dielectric layer;
• a passivation layer over said dielectric layer and on said metal pad, wherein a first opening in said passivation layer is over said metal pad;
• a polymer layer on said passivation layer wherein a second opening in said polymer layer is over said metal pad, and, wherein said polymer layer has a thickness greater than that of said passivation layer, that of said metal pad, that of said dielectric layer and that of said via and;
• a metal bump on said metal pad and on said polymer layer wherein said metal bump is connected to said metal pad through said second opening, and, wherein said metal bump comprises a sputtered copper layer over said metal pad and over said polymer layer, an electroplated nickel layer over said sputtered copper layer, over said metal pad and over said polymer layer, and a solder over the entire of a top surface of said electroplated nickel layer, over said metal pad and over said polymer layer.