Method of forming integrated circuit devices having n-MOSFET and p-MOSFET transistors with elevated and silicided source/drain structures

A method of forming an integrated circuit device, comprising:

• forming an n-FET gate dielectric on a substrate and a p-FET gate dielectric on the substrate;
• forming an n-FET gate electrode on the n-FET gate dielectric and a p-FET gate electrode on the p-FET gate dielectric, wherein the n-FET gate electrode and the p-FET gate electrode each comprise metal, wherein the n-FET gate dielectric is located between the n-FET gate electrode and the substrate at an n-FET channel region, and the p-FET gate dielectric is located between the p-FET gate electrode and the substrate at a p-FET channel region;
• forming an n-FET spacer structure adjacent to the n-FET gate electrode;
• forming a p-FET spacer structure adjacent to the p-FET gate electrode;
• forming an elevated n-FET source/drain structure adjacent to the n-FET gate electrode, such that the n-FET spacer structure is located at least partially between the elevated n-FET source/drain structure and the n-FET gate electrode;
• forming an elevated p-FET source/drain structure adjacent to the p-FET gate electrode, such that the p-FET spacer structure is located at least partially between the elevated p-FET source/drain structure and the p-FET gate electrode;
• and
• siliciding at least a first portion of the elevated n-FET source/drain structure and at least a first portion of the elevated p-FET source/drain structure in a source/drain-structure silicidation step, wherein at least a thermal treatment portion of the source/drain structure siliciding is performed simultaneously for the elevated n-FET source/drain structure and for the elevated p-FET source/drain structure;
• wherein the p-FET metal gate electrode is silicided in a p-FET gate-electrode silicidation step and the n-FET gate electrode is silicided in an n-FET gate-electrode silicidation step, wherein the source/drain-structure silicidation step is different from the p-FET gate-electrode silicidation step, the source/drain-structure silicidation step is different from the n-FET gate-electrode silicidation step, and the p-FET gate-electrode silicidation step is different from the n-FET gate-electrode silicidation step.

A method of forming an integrated circuit device, comprising:

• forming an n-FET gate dielectric on a substrate and a p-FET gate dielectric on the substrate, wherein the n-FET gate dielectric and the p-FET gate dielectric each comprise high-k dielectric material;
• forming an n-FET gate electrode structure on the n-FET gate dielectric and a p-FET gate electrode structure on the p-FET gate dielectric, wherein the n-FET gate dielectric is located between the n-FET gate electrode structure and the substrate at an n-FET channel region, and the p-FET gate dielectric is located between the p-FET gate electrode structure and the substrate at a p-FET channel region;
• forming an n-FET spacer structure adjacent to the n-FET gate electrode;
• forming an n-FET recess in the substrate adjacent to the n-FET spacer structure after forming the n-FET spacer structure;
• epitaxially growing an elevated n-FET source/drain structure from the substrate in the n-FET recess, wherein the epitaxial growing is performed using a first selective epitaxial growth process, such that the n-FET spacer structure is located at least partially between the elevated n-FET source/drain structure and the n-FET gate electrode;
• forming a p-FET spacer structure adjacent to the p-FET gate electrode;
• forming a p-FET recess in the substrate adjacent to the p-FET spacer structure;
• epitaxially growing an elevated p-FET source/drain structure from the substrate in the p-FET recess, wherein the epitaxial growing is performed using a first selective epitaxial growth process, such that the p-FET spacer structure is located at least partially between the elevated p-FET source/drain structure and the p-FET gate electrode;
• and
• simultaneously siliciding the elevated n-FET source/drain structure and the elevated p-FET source/drain structure.

A method of forming an integrated circuit device, comprising:

• forming an n-FET gate dielectric on a substrate and a p-FET gate dielectric on the substrate, wherein the n-FET gate dielectric and the p-FET gate dielectric each comprise high-k dielectric material;
• forming an n-FET gate electrode structure on the n-FET gate dielectric and a p-FET gate electrode structure on the p-FET gate dielectric, wherein the n-FET gate dielectric is located between the n-FET gate electrode structure and the substrate at an n-FET channel region, and the p-FET gate dielectric is located between the p-FET gate electrode structure and the substrate at a p-FET channel region;
• forming an n-FET spacer structure adjacent to the n-FET gate electrode;
• forming a p-FET spacer structure adjacent to the p-FET gate electrode;
• forming an elevated n-FET source/drain structure adjacent to the n-FET gate electrode, such that the n-FET spacer structure is located at least partially between the elevated n-FET source/drain structure and the n-FET gate electrode;
• forming a p-FET recess in the substrate adjacent to the p-FET spacer structure;
• forming an elevated p-FET source/drain structure extending from the substrate in the p-FET recess, such that the p-FET spacer structure is located at least partially between the elevated p-FET source/drain structure and the p-FET gate electrode;
• and
• simultaneously siliciding the elevated n-FET source/drain structure and the elevated p-FET source/drain structure;
• also simultaneously siliciding the p-FET gate electrode structure, n-FET gate electrode structure, or both, while siliciding the elevated n-FET source/drain structure and the elevated p-FET source/drain structure;
• selecting an n-FET source/drain structure height to control a silicidation depth of the n-FET source/drain structure so that the silicidation depth of the n-FET source/drain structure is not more than about 250 angstroms below a top surface of the substrate;
• and
• selecting a p-FET source/drain structure height to control a silicidation depth of the p-FET source/drain structure so that the silicidation depth of the p-FET source/drain structure is not more than about 250 angstroms below the top surface of the substrate.