Active inductive load that enhances circuit bandwidth

An active load, comprising:

• a current source configured to provide a constant bias current;
• a first resistive element configured to receive the constant current and provide a bias voltage;
• an n-channel metal oxide semiconductor (NMOS) transistor comprising an input and an output, wherein the bias voltage is provided between the input and the output to bias the NMOS transistor, wherein an impedance at the output increases to provide inductive peaking at frequencies higher than a zero frequency that is based on the first resistive element and an internal capacitance of the NMOS transistor;
• and
• a second resistive element coupled to the output of the NMOS transistor and configured to provide a constant load resistance between the drain and source of the NMOS transistor, wherein the impedance at the output rises to a maximum impedance of a parallel combination of the first resistive element, the second resistive element, and an internal resistance of the NMOS transistor.

An active load, comprising:

• means for sourcing a constant bias current;
• means for providing a bias voltage based on the constant bias current;
• means for biasing an n-channel metal oxide semiconductor (NMOS) transistor via the bias voltage to maintain headroom;
• means for providing an inductive impedance that enhances circuit bandwidth;
• and
• means for providing a constant load resistance between drain and source of the NMOS transistor.

A method for providing an active load, comprising:

• sourcing a constant bias current;
• providing a bias voltage across a resistive element via the constant bias current;
• biasing an n-channel metal oxide semiconductor (NMOS) transistor via the bias voltage to maintain headroom;
• providing an inductive impedance to enhance circuit bandwidth;
• and
• providing a constant load resistance between drain and source of the NMOS transistor.

A method for providing an active load, comprising:

• sourcing a constant bias current;
• receiving the constant bias current at a first resistive element to provide a bias voltage across the first resistive element based on the constant bias current;
• biasing an n-channel metal oxide semiconductor (NMOS) transistor via the bias voltage;
• outputting at an output of the NMOS transistor an impedance that increases to provide inductive peaking beyond a zero frequency that is based on the first resistive element and an internal capacitance of the NMOS transistor;
• and
• outputting at the output of the NMOS transistor the impedance that rises to a maximum impedance of a parallel combination of the first resistive element, a second resistive element that is coupled to the output and configured to provide a constant load resistance between the drain and source of the NMOS transistor, and an internal resistance of the NMOS transistor.