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US 7,453,122 B2Granted
SOI MOSFET device with reduced polysilicon loading on active area
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorShao-Chang Huang
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Abstract
Silicon-on-insulator (SOI) devices with reduced polysilicon loading on an active area uses at least one dielectric layer resistant to silicidation to separate at least one body contact region from source/drain regions, thus reducing gate capacitance and improving device performance. The SOI devices may be used in full depletion type transistors or partial depletion type transistors.
Claims12
A silicon-on-insulator (SOI) device, comprising:
- a SOI substrate having an active area, wherein said SOI substrate comprises a semiconductor layer overlying an insulator layer;
- at least one gate structure comprising a gate dielectric layer and a gate electrode layer over said semiconductor layer of said active area;
- a source region and a drain region in said semiconductor layer of said active area and separated from each other;
- a dielectric layer resistant to silicidation with a bottom surface overlying a top surface of said semiconductor layer of said active area, wherein said dielectric layer resistant to silicidation is made of a material different from said gate dielectric layer;
- and
- a body contact region in said semiconductor layer of said active area and separated from said source region and said drain region by a region underlying said dielectric layer resistant to silicidation, wherein said body contact region is in contact with a metal-silicide layer.
3 more elements
Dependencies are inferred from the claim text.