Method for applying a stress layer to a semiconductor device and device formed therefrom
AssigneeDSM Solutions, Inc.
InventorAshok K. Kapoor
Life of this patent
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Abstract
A semiconductor device includes a substrate of semiconductor material. A source region, a drain region, and a conducting region of the semiconductor device are formed in the substrate and doped with a first type of impurities. The conducting region is operable to conduct current between the drain region and the source region when the semiconductor device is operating in an on state. A gate region is also formed in the substrate and doped with a second type of impurities. The gate region abuts a channel region of the conducting region. A stress layer is deposited on at least a portion of the conducting region. The stress layer applies a stress to the conducting region along a boundary of the conducting region that strains at least a portion of the conducting region.
Claims20
A semiconductor device, comprising:
- a substrate formed of semiconductor material;
- a source region formed in the substrate and doped with a first type of impurities;
- a drain region formed in the substrate and doped with the first type of impurities, the drain region spaced apart from the source region;
- a conducting region formed between the source region and the drain region and doped with the first type of impurities, the conducting region operable to conduct current between the drain region and the source region when the semiconductor device is operating in an on state;
- a channel region formed in the conducting region;
- a gate region formed in the substrate and doped with a second type of impurities, the gate region abutting the channel region;
- and
- a stress layer deposited on at least a portion of the conducting region, wherein the stress layer applies a stress to the conducting region along a boundary of the conducting region that strains at least a portion of the conducting region;
- the semiconductor device comprises a junction field effect transistor (JFET).
A method for creating a stress within a semiconductor device, comprising:
- forming a source region doped with a first type of impurities in a semiconductor substrate;
- forming a drain region doped with the first type of impurities in the semiconductor substrate, the drain region spaced apart from the source region;
- forming a conducting region between the source region and the drain region the conducting region doped with the first type of impurities and operable to conduct current between the drain region and the source region when the semiconductor device is operating in an on state;
- forming a channel region within the conducting region;
- forming a gate region doped with a second type of impurities, the gate region abutting the channel region;
- and
- depositing a stress layer on at least a portion of the conducting region that applies a stress to the conducting region along a boundary of the conducting region, wherein the stress strains at least a portion of the conducting region;
- the semiconductor device comprises a junction field effect transistor (JFET).
Dependencies are inferred from the claim text.