Semiconductor device including a semiconductor substrate formed with a shallow impurity region
AssigneeKabushiki Kaisha Toshiba
InventorTakayuki Ito
Life of this patent
Estimating the term…
Abstract
A method of manufacturing a semiconductor device includes forming isolation regions, a gate insulator film and gate electrodes, implanting in the silicon substrate with impurity ions, annealing to recover crystallinity of the implanted silicon substrate without diffusing the impurity ions, depositing an interlayer insulator film on the isolation regions, the silicon substrate, and the gate electrodes, and heating the silicon substrate by irradiating a light having a wavelength that the light is absorbed by the silicon substrate without being absorbed by the interlayer insulator film, activating the impurity ions so as to form source and drain regions.
Claims9
A semiconductor device comprising:
- a silicon substrate;
- a plurality of isolation regions provided on the surface of the silicon substrate;
- a gate insulator film provided on the silicon substrate;
- a gate electrode deposited on the gate insulator film;
- source and drain regions provided on the surface of the silicon substrate and having a conductivity different from that of the silicon substrate;
- and
- an auxiliary layer which is a silicon nitride layer provided at a location lower than the gate insulator film, the auxiliary layer being located between the surface and the underside of the silicon substrate and closer to the underside, and the auxiliary layer failing to border the underside.
A semiconductor device comprising:
- a silicon substrate;
- a plurality of isolation regions provided on the surface of the silicon substrate;
- a gate insulator film provided in contact with the silicon substrate;
- a gate electrode deposited on the gate insulator film;
- source and drain regions provided on the surface of the silicon substrate and having a conductivity different from that of the silicon substrate;
- and
- an auxiliary layer which is a silicon carbide layer provided at a location lower than the gate insulator film, the plurality of isolation regions, and the source and drain regions.
Dependencies are inferred from the claim text.