Integrated semiconductor memory and method for operating a semiconductor memory

A method for operating a semiconductor memory device that includes at least one memory cell, at least one sense amplifier and a pair of bit lines connected to each sense amplifier, wherein each memory cell includes a selection transistor and a storage capacitor, each storage capacitor includes a first capacitor electrode and a second capacitor electrode, each selection transistor includes a first source/drain region that is connected by a first contact connection to one bit line of a pair of bit lines corresponding with a respective memory cell and a second source/drain region that is conductively connected to the first capacitor electrode of the storage capacitor of the respective memory cell, and the second capacitor electrode of each storage capacitor is connected by a second contact connection to the other bit line of the pair of bit lines corresponding with the respective memory cell, wherein the method comprises:

• opening a selection transistor of a memory cell;
• and
• applying a potential difference between potentials of the two bit lines of the pair of bit lines connected to the sense amplifier;
• wherein the first capacitor electrode of the storage capacitor of the memory cell is biased with a first potential via a bit line of the pair of bit lines that is connected to a first connection of the sense amplifier and via the first contact connection, and the second capacitor electrode of the storage capacitor of the memory cell is biased with a second potential via a bit line of the pair of bit lines that is connected to a second connection of the sense amplifier and via the second contact connection.

A method of manufacturing a memory device, the method comprising:

• forming at least one memory cell comprising a selection transistor and a storage capacitor, wherein the storage capacitor of each memory cell includes a first capacitor electrode and a second capacitor electrode, the selection transistor of each memory cell includes a first source/drain region that is connected to one bit line of a pair of bit lines corresponding with the memory cell and a second source/drain region that is conductively connected to the first capacitor electrode of the storage capacitor of the memory cell, and the second capacitor electrode of the storage capacitor of each memory cell is directly connected to and permanently short-circuited with the other bit line of the pair of bit lines corresponding with the memory cell;
• and
• connecting each pair of bit lines corresponding with each memory cell to a respective sense amplifier, wherein the pair of bit lines that are connected to each sense amplifier are biased by the respective sense amplifier such that an existing potential difference between a potential of one bit line and a potential of the other bit line of the pair is increased, with one of the bit lines of the pair being biased with a first potential that is output at a first connection of the respective sense amplifier and the other bit line of the pair being biased with a second potential that is output at a second connection of the respective sense amplifier.