US 7,443,708 B2Granted

Low resistance plate line bus architecture

AssigneeTexas Instruments Incorporated

InventorsSudhir Kumar Madan, Sung-Wei Lin, John Fong

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Abstract

An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.

Claims45

Dependent claims

An array of FeRAM memory cells, comprising:

a plurality of columns arranged along a bit line direction and a plurality of rows arranged along a word line direction;
a plurality of plate lines arranged along a word line direction;
a common plate line driver connected to, and configured to drive the plurality of plate lines, thereby globally interconnecting the plate lines in the array;
first and second FeRAM memory cells arranged in the bit line direction in a first column, the first and second FeRAM memory cells operably associated with different plate lines;
and
third and fourth FeRAM memory cells arranged in the bit line direction in a second column, the third and fourth FeRAM memory cells operably associated with different plate lines,
wherein a plate line of the first FeRAM memory cell is locally interconnected to a plate line of the second FeRAM memory cell by a first local plate line interconnection, and a plate line of the third FeRAM memory cell is locally interconnected to a plate line of the fourth FeRAM memory cell by a second local plate line interconnection, thereby providing an FeRAM memory array having a reduced plate line resistance.

4 more elements

A memory array, comprising:

a plurality of FeRAM memory cells arranged in rows of memory cells along a word line direction and columns of memory cells along a bit line direction;
a plurality of plate lines associated with the rows of memory cells;
a common plate line driver connected to, and configured to drive the plurality of plate lines, thereby globally interconnecting the plate lines in the array;
first and second FeRAM memory cells arranged adjacent to each other in the bit line direction in a first column, the first and second FeRAM memory cells operably associated with different plate lines;
and
third and fourth FeRAM memory cells arranged adjacent to each other in the bit line direction in a second column, the third and fourth FeRAM memory cells operably associated with different plate lines;
wherein a plate line of the first FeRAM memory cell is locally interconnected to a plate line of the second FeRAM memory cell by a first local plate line interconnection, and a plate line of the third FeRAM memory cell is locally interconnected to a plate line of the fourth FeRAM memory cell by a second local plate line interconnection, thereby providing an FeRAM memory array having a reduced plate line resistance.

4 more elements

Dependencies are inferred from the claim text.