Multi-threshold MIS integrated circuit device and circuit design method thereof
AssigneeFujitsu Limited
InventorSatoru Miyagi
Life of this patent
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Abstract
On a chip 50A, disposed are macro cell 20A not including a virtual power supply line and a leak-current-shielding MOS transistor of a high threshold voltage, and a leak-current-shielding MOS transistor cell 51 of the high threshold voltage. The transistor cell 51 has a gate line 51G which is coincident with the longitudinal direction of the cell, is disposed along a side of a rectangular cell frame of the macro cell 20A, and has a drain region 51D connected to VDD pads 60 and 61 for external connection, the gate line 51G connected to an I/O cell 73 and a source region 51S connected to a VDD terminal of the macro cell 20A. This VDD terminal functions as a terminal of a virtual power supply line V_VDD.
Claims8
A multi-threshold MIS integrated circuit design method, comprising the steps of:
- disposing a first macro including an internal circuit and a virtual power supply line connected to the internal circuit, the internal circuit including a first MIS transistor cell having a first threshold voltage;
- disposing a leak-current-shielding MIS transistor cell along a side of a macro frame of the first macro, the leak-current-shielding MIS transistor cell having a second threshold voltage higher than the first threshold voltage, the leak-current-shielding MIS transistor cell having a gate line and having a longitudinal direction coincident with the gate line;
- and
- connecting one and another ends of a current path of the leak-current-shielding MIS transistor cell to a power supply line and the virtual power supply line, respectively, and connecting the gate line to a power control line.
Dependencies are inferred from the claim text.