Non-volatile memory devices including divided charge storage structures

A semiconductor memory device, comprising:

• a substrate having first and second source/drain regions therein and a channel region therebetween;
• first and second charge storage layers on the channel region;
• a first insulating layer on the channel region between the first and second charge storage layers;
• a lower gate electrode on the first insulating layer opposite the channel region and between inner sidewalls of the first and second charge storage layers, wherein the lower gate electrode extends away from the substrate beyond the first and second charge storage layers;
• second and third insulating layers extending from adjacent the inner sidewalls of the first and second charge storage layers along portions of the lower gate electrode beyond the first and second charge storage layers;
• first and second control gate electrodes on the respective first and second charge storage layers;
• and
• an upper gate electrode on the lower gate electrode between the first and second control gate electrodes,
• wherein the first, second, and third insulating layers comprise oxide layers.

A semiconductor memory device, comprising:

• a semiconductor substrate;
• a fin-shaped active region protruding from the substrate and having first and second source/drain regions therein and a channel region therebetween;
• first and second charge storage layers on opposing sidewalls of the channel region and on a surface therebetween;
• a first insulating layer on the opposing sidewalls and the surface therebetween of the channel region and between the first and second charge storage layers;
• a lower gate electrode on the first insulating layer opposite the channel region on the opposing sidewalls and the surface therebetween of the channel region;
• second and third insulating layers extending from adjacent inner sidewalls of the first and second charge storage layers along portions of the lower gate electrode beyond the first and second charge storage layers;
• first and second control gate electrodes on the respective first and second charge storage layers on the opposing sidewalls and the surface therebetween of the channel region;
• and
• an upper gate electrode on the lower gate electrode between the first and second control gate electrodes.