Semiconductor device manufacturing methods

A method of manufacturing a semiconductor device including a high-voltage device region and a low-voltage device region, the method comprising:

• forming a gate pattern on the high-voltage device region and on the low-voltage device region;
• forming a first lightly doped drain (LDD) structure in a first portion of the high-voltage device region on opposite sides of a first gate of the gate pattern by implanting first ions into the first portion of the high-voltage device region, wherein the first ions are implanted to a concentration of 1×1013 to about 7×1013 atoms/cm2;
• forming a second LDD structure in a second portion of the high-voltage device region on opposite sides of a second gate of the gate pattern by implanting second ions into the second portion of the high-voltage device region and simultaneously forming a third LDD structure in a portion of the low-voltage device region on opposite sides of a third gate of the gate pattern by implanting second ions into the low-voltage device region, wherein the second ions are implanted to a concentration of 5×1014 to 5×1015 atoms/cm2;
• forming a spacer at a side surface of the gate pattern;
• forming a source region and a drain source at field regions disposed at the opposite sides of the gate pattern, respectively;
• and
• forming a metal layer on a front surface of the substrate including the gate pattern.