US 7,412,677 B1 · Detecting reducible registers

Abstract

Reducible registers are determined to optimize a sequential circuit. A screening method tests one or more sets of registers where the registers of each set are assumed to satisfy a logic condition. The tests determine if the logic condition holds. If the logic condition of a set is found to be violated, the registers may be moved to another set having a different logic condition or removed completely. The registers remaining are potentially reducible. The reducibility of the registers is verified via Boolean analysis by verifying the logic conditions of a register set for each register. If a register does not pass verification, it then may be moved to a different set having a different logic condition or removed completely. The sets that pass verification are reducible.

Claims30

Dependent claims

A method for optimizing a sequential circuit, the method comprising:

defining a set R1 having a first logic condition;
populating the set R1 with registers assumed to satisfy the first logic condition;
testing a plurality of registers in the set R1 for a violation of the first logic condition of the set R1;
removing, from the set R1, at least one register violating the first logic condition of the set R1;
and
verifying whether the registers remaining in the set R1 satisfy the first logic condition.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

11/360,739Filed 22 Feb 2006

Granted

12 Aug 2008

Term ends

Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 30/3323
Design verification, e.g. functional simulation or model checking: using formal methods, e.g. equivalence checking or property checking
G06F 2119/12
Details relating to the type or aim of the analysis or the optimisation: timing analysis or timing optimisation
G06F
Computing and data processing

Detecting reducible registers

Life of this patent

Detecting reducible registers

Life of this patent

Abstract

Claims30