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AssigneeJasper Design Automation, Inc.
InventorsVigyan Singhal, Brajesh Arora, Yann Antonioli
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A method and apparatus for measuring the progress of a formal verification process using an analysis region, and measures the effectiveness of the current set of properties/requirements in verifying different portions of logic within the design. The present invention applies the concept of analysis region to analyze the properties/requirements for a design. The analysis region can be expanded or contracted either manually or automatically based upon the results of the analysis. The present invention generates a visual display that is available to the user that represents the amount of source code in the analysis region for a given property or multiple properties in comparison to the maximum possible analysis region. The present invention can display this information in a bar graph format, on a line-by-line basis for the source code and on a waveform display, for example.
A computer based method for identifying verification progress information from an analysis region for one or more properties to be verified in a circuit model verification environment comprising the steps of:
A computer based system for identifying verification progress information from an analysis region for one or more properties to be verified in a circuit model verification environment comprising:
Dependencies are inferred from the claim text.