Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit

A computer-readable memory having computer-readable program code embodied therein for causing a computer system to perform a method that generates broadcast scan patterns to test a scan-based integrated circuit through a broadcaster and a compactor, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, the scan chain inputs connected to the broadcaster, the scan chain outputs connected to the compactor, said method comprising the steps of:

• a) compiling the HDL (hardware description language) code modeled at register-transfer level (RTL) or gate-level that represents said scan-based integrated circuit, said broadcaster, and said compactor into a sequential circuit model;
• b) establishing a set of input constraints on first selected scan cells based on the predetermined values to be assigned on said broadcaster and second selected scan cells based on the predetermined values to be assigned on said compactor during each shift cycle or between test sessions;
• c) transforming said sequential circuit model into an equivalent combinational circuit model by further duplicating or expanding said broadcaster into third selected scan cells and said compactor into fourth selected scan cells in said equivalent combinational circuit model;
• d) generating said broadcast scan patterns according to said set of input constraints to avoid X-impact and aliasing;
• and
• e) re-assigning a new set of input constraints and repeating step (d) until a predetermined limiting criterion is met,
• wherein said broadcaster is selectively an LFSR (linear-feedback shift register) based sequential circuit, or a combinational logic network comprising one or more logic gates, including AND gates, OR gates, NAND gates, NOR gates, XOR gates, XNOR gates, multiplexers, buffers, inverters, or any combination of the above;
• and wherein said compactor is selectively an XOR network comprising one or more XOR gates, and
• wherein said broadcaster further comprises using a plurality of scan connectors to connect the outputs of said LFSR based sequential circuit or said combinational logic network to selected scan chain inputs in said scan-based integrated circuit.

An electronic design automation system comprising:

• a processor;
• a bus coupled to said processor;
• and
• a computer-readable memory coupled to said bus and having computer-readable program code stored therein for causing said electronic design automation system to perform a method that generates broadcast scan patterns to test a scan-based integrated circuit through a broadcaster and a compactor, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, the scan chain inputs connected to the broadcaster, the scan chain outputs connected to the compactor, said method comprising the steps of:
• a) compiling the HDL (hardware description language) code modeled at register-transfer level (RTL) or gate-level that represents said scan-based integrated circuit, said broadcaster, and said compactor into a sequential circuit model;
• b) establishing a set of input constraints on first selected scan cells based on the predetermined values to be assigned on said broadcaster and second selected scan cells based on the predetermined values to be assigned on said compactor during each shift cycle or between test sessions;
• c) transforming said sequential circuit model into an equivalent combinational circuit model by further duplicating or expanding said broadcaster into third selected scan cells and said compactor into fourth selected scan cells in said equivalent combinational circuit model;
• d) generating said broadcast scan patterns according to said set of input constraints to avoid X-impact and aliasing;
• and
• e) re-assigning a new set of input constraints and repeating step (d) until a predetermined limiting criterion is met,
• wherein said broadcaster is selectively an LFSR (linear-feedback shift register) based sequential circuit, or a combinational logic network comprising one or more logic gates, including AND gates, OR gates, NAND gates, NOR gates, XOR gates, XNOR gates, multiplexers, buffers, inverters, or any combination of the above;
• and wherein said compactor is selectively an XOR network comprising one or more XOR gates, and
• wherein said broadcaster further comprises using a plurality of scan connectors to connect the outputs of said LFSR based sequential circuit or said combinational logic network to selected scan chain inputs in said scan-based integrated circuit.

A method that synthesizes a broadcaster and a compactor to test a scan-based integrated circuit, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, the scan chain inputs coupled to the broadcaster and the scan chain outputs coupled to the compactor, said method comprising the steps of:

• a) compiling the HDL (hardware description language) code modeled at RTL (register-transfer level) or gate-level that represents said scan-based integrated circuit into a sequential circuit model;
• b) establishing constraints on said broadcaster, said compactor, and for stitching;
• c) synthesizing said broadcaster according to said constraints specified on said broadcaster;
• d) synthesizing said compactor according to said constraints specified on said compactor;
• e) stitching said broadcaster and said compactor on said sequential circuit model according to said constraints specified for stitching;
• and
• f) generating synthesized HDL code modeled at RTL or gate-level,
• wherein said broadcaster is selectively an LFSR (linear-feedback shift register) based sequential circuit, or a combinational logic network comprising one or more logic gates, including AND gates, OR gates, NAND gates, NOR gates, XOR gates, XNOR gates, multiplexers, buffers, inverters, or any combination of the above, and
• wherein said broadcaster further comprises using a plurality of scan connectors to connect the outputs of said LFSR based sequential circuit or said combinational logic network to selected scan chain inputs in said scan-based integrated circuit.