Generation of graphical design representation from a design specification data file

An apparatus for generating a block diagram of an electronic circuit design, comprising:

• means for identifying from an input textual description of the electronic circuit design, each multi-master bus, bus master of a multi-master bus, bus slave of a multi-master bus, and input/output port;
• means for representing diagrammatic placement of each input/output port about a perimeter of a first area;
• means for representing a bus area, a master area, and a slave area within the first area;
• means for representing in the memory, placement in the bus area of each multi-master bus;
• means for representing placement in the master area of each bus master of a multi-master bus, wherein no bus master is placed between another bus master and a multi-master bus;
• means for representing a group of bus slaves of a multi-master bus, wherein each bus slave in the group has a slave connection to the multi-master bus and no other connection to any bus master of the multi-master bus;
• means for representing placement of the group of bus slaves as a single block in the bus area, wherein the group is diagrammatically aligned with a bus master of the multi-master bus to which the group of bus slaves is connected;
• means for representing connections between each multi-master bus and each bus master of the multi-master bus and a connection between the multi-master bus and the group of bus slaves with connection lines;
• and
• means for outputting a diagrammatic representation consistent with the representations of the placement of each identified multi-master bus, bus master, bus slave, and connections.

An article of manufacture, comprising:

• a processor-readable medium configured with instructions executable by a processor for generating a block diagram of an electronic circuit design by performing steps including,
• identifying by the processor from an input textual description of the electronic circuit design, each multi-master bus, bus master of a multi-master bus, bus slave of a multi-master bus, and input/output port;
• representing in a memory coupled to the processor, diagrammatic placement of each input/output port about a perimeter of a first area;
• representing in the memory, a bus area, a master area, and a slave area within the first area;
• representing in the memory, placement in the bus area of each multi-master bus;
• representing in the memory, placement in the master area of each bus master of a multi-master bus, wherein no bus master is placed between another bus master and a multi-master bus;
• representing in the memory, a group of bus slaves of a multi-master bus, wherein each bus slave in the group has a slave connection to the multi-master bus and no other connection to any bus master of the multi-master bus;
• representing in the memory, placement of the group of bus slaves as a single block in the bus area, wherein the group is diagrammatically aligned with a bus master of the multi-master bus to which the group of bus slaves is connected;
• representing in the memory, connections between each multi-master bus and each bus master of the multi-master bus and a connection between the multi-master bus and the group of bus slaves with respective connection lines;
• and
• outputting a diagrammatic representation consistent with the representations of the placement of each identified multi-master bus, bus master, bus slave, and connections.