System and method for testing circuitry on a wafer

A method for testing a plurality of dice on a semiconductor wafer, said method comprising:

• receiving test data at a semiconductor wafer having a plurality of dice fabricated thereon, wherein said receiving comprises receiving said test data from a test system implemented on at least one dedicated die of said semiconductor wafer;
• and
• communicating said test data to multiple of said plurality of dice concurrently via a communication system fabricated on said semiconductor wafer that interconnects said multiple dice, wherein at least a portion of said test data is output test data responsive to input test data and is communicated from an output of at least one of said multiple dice to an input of at least one other of said multiple dice.

A system for testing a plurality of dice on a semiconductor wafer, said system comprising:

• circuitry fabricated on a semiconductor wafer, wherein said circuitry is defined by a repeatable reticle pattern and wherein said circuitry comprises a communication system interconnecting a plurality of dice on said semiconductor wafer for concurrently communicating test data to said plurality of dice, wherein said communication system interconnects said plurality of dice to communicate test data which is outputted from at least one of said plurality of dice and is inputted to at least one other of said plurality of dice.