Method and apparatus for broadcasting test patterns in a scan based integrated circuit

A method that accepts a virtual scan pattern stored in an ATE (automatic test equipment) for generating broadcast scan pattern in a broadcaster having n broadcast scan inputs and m outputs to test a random access scan based (RAS-based) integrated circuit;

• where n<m. the RAS-based integrated circuit containing an m-input and m-output RAS core organized in an array of RAS cells so that each row is randomly and uniquely addressable, the inputs to the RAS core connected to the outputs of the broadcaster, the broadcaster comprising a combinatonal logic network that includes one or more logic gates, including AND gates, OR gates, NAND gates, NOR gates, XOR gates, XNOR gates, multiplexers, buffers, inverters, or any combination of the above, the outputs from the RAS core connected to the inputs of a compactor having m inputs and k outputs for compacting selected outputs of said RAS core for comparison in said ATE, where k<m, said method comprising:
• a) placing said broadcaster between said ATE and said RAS-based integrated circuit;
• b) transmitting a new said virtual scan pattern stored in said ATE to said broadcaster for generating said broadcast scan pattern to test manufacturing faults in said RAS-based integrated circuit;
• and
• c) comparing the test response of said RAS-based integrated circuit with the expected test response.

A method that accepts virtual scan patterns stored in an ATE (automatic test equipment) for generating broadcast scan patterns in a broadcaster having n broadcast scan inputs and m outputs to test a random access scan based (RAS-based) integrated circuit, where n<m, the RAS-based integrated circuit containing an m-input and m-output RAS core orcranized in an array of RAS cells so that each row is randomly and uniquely addressable, the inputs to the RAS core connected to the outputs of the broadcaster, the broadcaster comprising a combinational logic network that includes one or more logic gates, including AND gates, OR gates, NAND gates, NOR gates, XOR gates, XNOR gates, multiplexers, buffers, inverters, or any combination of the above, the outputs from the RAS core connected to the inputs of a compactor having m inputs and k outputs for compacting selected outputs of said RAS core for comparison in said ATE, where k<m, said system comprising:

• a) using simulation, modeling said broadcaster in said ATE;
• b) applying a new said virtual scan pattern stored in said ATE to generate said broadcast scan pattern using the simulated broadcaster model;
• c) transmitting said broadcast scan pattern generated by said broadcaster in said ATE to said scan cells in said RAS-based integrated circuit for testing manufacturing faults in said RAS-based integrated circuit;
• and
• d) comparing the test response of said RAS-based integrated circuit with the expected test response.

A method that accepts a virtual scan pattern stored in an ATE (automatic test equipment) for generating a broadcast scan pattern in a broadcaster having n broadcast scan inputs and m outputs to test a scan-based integrated circuit, where n<m. the broadcaster accepting the virtual scan patterns via broadcast scan inputs for generating the broadcast scan patterns, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells, the scan chains coupled to the broadcaster, the broadcaster comprising a multiplexer network directly connected to said broadcast scan inputs, said multiplexer network having selected outputs and selected scan outputs of all said scan chains connected to selected scan inputs of all said scan chains, said method comprising:

• a) placing said broadcaster between said ATE and said scan-based integrated circuit;
• b) transmitting said virtual scan pattern stored in said ATE to said broadcaster for generating said broadcast scan pattern to test manufacturing faults in said scan-based integrated circuit;
• and
• c) comparing a test response of said scan-based integrated circuit with an expected test response.

A method that accepts a virtual scan pattern stored in an ATE (automatic test equipment) for generating a broadcast scan pattern in a broadcaster having n broadcast scan inputs and m outputs to test a scan-based integrated circuit, where n<m. the broadcaster accepting the virtual scan patterns via broadcast scan inputs for generating the broadcast scan patterns, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells, the scan chains coupled to the broadcaster, the broadcaster comprising a multiplexer network directly connected to said broadcast scan inputs, said multiplexer network having selected outputs and selected scan outputs of all said scan chains connected to selected scan inputs of all said scan chains, said method comprising:

• a) using simulation, modeling said broadcaster in said ATE;
• b) applying said virtual scan pattern stored in said ATE to generate said broadcast scan pattern using the simulated broadcaster model;
• c) transmitting said broadcast scan pattern generated by said broadcaster in said ATE to said scan chains in said scan-based integrated circuit for testing manufacturing faults in said scan-based integrated circuit;
• and
• d) comparing a test response of said scan-based integrated circuit with an expected test response.