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US 7,412,630 B2Granted
Trace control from hardware and software
AssigneeMIPS Technologies, Inc.
InventorRadhika Thekkath
Life of this patent
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Abstract
A system and method for program counter and data tracing is disclosed. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.
Claims9
A tracing control method, comprising:
- initiating first tracing of data in a first processor mode of an embedded processor, said first tracing being from said embedded processor to a trace memory during execution of a program that includes a plurality of instructions, said first tracing initiation being based on a first trace control command embodied in one or more instructions of said program;
- and
- halting second tracing of data in a second processor mode of said embedded processor based upon a second trace control command embodied in one or more instructions of said program without disabling said first tracing;
- wherein said first trace control command and said second trace control command are operative to trigger tracing on for said first tracing of data and off for said second tracing of data without using one or more breakpoints.
1 more element
A computer program product comprising:
- computer-readable program code for causing a computer to describe an embedded processor, said embedded processor including a processor core for executing instructions, and trace generation logic that is operative to generate trace data for said instructions executing in said processor core, said trace generation logic capable of applying said trace data to a trace memory and being controlled by hardware input signals and by a software-settable trace control register adapted to be set by at least one trace control command embodied in instructions of a program to be traced, wherein said software-settable trace control register includes a first field operative to enable tracing in a first processor mode of said embedded processor, and a second field operative to disable tracing in a second processor mode of said embedded processor without disabling tracing in said first processor mode;
- and
- a computer-usable medium configured to store the computer-readable program code, wherein said embedded processor is operative to utilize said at least one trace control command to trigger tracing on and off without requiring the use of one or more breakpoints.
A computer-readable storage medium, comprising executable instructions to:
- cause a computer to describe an embedded processor, said embedded processor including a processor core for executing instructions, and trace generation logic that is operative to generate trace data for said instructions executing in said processor core, said trace generation logic capable of applying said trace data to a trace memory and being controlled by hardware input signals and by a software-settable trace control register adapted to be set by at least one trace control command embodied in instructions of a program to be traced, wherein said software-settable trace control register includes a first field operative to enable tracing in a first processor mode of said embedded processor, and a second field operative to disable tracing in a second processor mode of said embedded processor without disabling tracing in said first processor mode;
- wherein said embedded processor is operative to utilize said at least one trace control command to trigger tracing on and off without requiring the use of one or more breakpoints.
Dependencies are inferred from the claim text.