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US 7,412,617 B2Granted
Phase frequency detector with limited output pulse width and method thereof
AssigneeMediatek Inc.
InventorHsiang-Hui Chang
Life of this patent
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Abstract
Phase frequency detectors with limited output pulse width and related methods are disclosed. The proposed phase frequency detector generates a first output signal and a second output signal corresponding to phase difference or frequency difference between a first signal and a second signal. When the phase difference between the first and second signals is greater than a predetermined delay, the pulse width of the first output signal is limited, so that the proposed phase frequency detector has a limited equivalent output pulse width.
Claims22
A phase frequency detector comprising:
- a first edge detector for detecting first-type edges of a first signal to generate a first detection signal and for changing the level of the first detection signal according to a first control signal;
- a first latch unit coupled to the first edge detector for latching the first detection signal to generate a first output signal and for changing the level of the first output signal according to a third control signal;
- a first delay unit coupled to the first latching unit for delaying the first output signal to generate a first delayed signal;
- a second edge detector for detecting the first-type edges of a second signal to generate a second detection signal and for changing the level of the second detection signal according to a second control signal;
- a second latch unit coupled to the second edge detector for latching the second detection signal to generate a second output signal and for changing the level of the second output signal according to the third control signal;
- a second delay unit coupled to the second latching unit for delaying the second output signal to generate a second delayed signal;
- a combination logic coupled to the first and second latch units for performing a predetermined logical operation on the first output signal and the second output signal to generate the third control signal;
- a first logic unit coupled to the first delay unit, the combination logic, and the first edge detector, for performing a first logical operation on the first delayed signal and the third control signal to generate the first control signal;
- and
- a second logic unit coupled to the second delay unit, the combination logic, and the second edge detector, for performing a second logical operation on the second delayed signal and the third control signal to generate the second control signal.
7 more elements
A method for generating a first output signal and a second output signal corresponding to phase difference or frequency difference between a first signal and a second signal, the method comprising:
- detecting first-type edges of the first signal to generate a first detection signal;
- changing the level of the first detection signal according to a first control signal;
- latching the first detection signal to generate a first output signal;
- changing the level of the first output signal according to a third control signal;
- delaying the first output signal to generate a first delayed signal;
- detecting the first-type edges of the second signal to generate a second detection signal;
- changing the level of the second detection signal according to a second control signal;
- latching the second detection signal to generate a second output signal;
- changing the level of the second output signal according to the third control signal;
- delaying the second output signal to generate a second delayed signal;
- performing a predetermined logical operation on the first output signal and the second output signal to generate the third control signal;
- performing a first logical operation on the first delayed signal and the third control signal to generate the first control signal;
- and
- performing a second logical operation on the second delayed signal and the third control signal to generate the second control signal.
11 more elements
A signal generating module comprising:
- a first latch unit for latching a first input signal to generate a first latched signal and for changing the level of the first latched signal according to a control signal;
- a first delay unit coupled to the first latching unit for delaying the first latched signal to generate a first delayed signal;
- a second latch unit for latching a second input signal to generate a second latched signal and for changing the level of the second latched signal according to the control signal;
- a second delay unit coupled to the second latching unit for delaying the second latched signal to generate a second delayed signal;
- a combination logic coupled to the first and second latch units for performing a predetermined logical operation on the first latched signal and the second latched signal to generate the control signal;
- a first logic unit, coupled to the first delay unit and the combination logic, for performing a first logical operation on the first delayed signal and the control signal to generate a first signal;
- and
- a second logic unit, coupled to the second delay unit and the combination logic, for performing a second logical operation on the second delayed signal and the control signal to generate a second signal.
5 more elements
A signal generation method comprising:
- latching a first input signal to generate a first latched signal;
- changing the level of the first latched signal according to a control signal;
- delaying the first latched signal to generate a first delayed signal;
- latching a second input signal to generate a second latched signal;
- changing the level of the second latched signal according to the control signal;
- delaying the second latched signal to generate a second delayed signal;
- performing a predetermined logical operation on the first latched signal and the second latched signal to generate the control signal;
- performing a first logical operation on the first delayed signal and the control signal to generate a first signal;
- and
- performing a second logical operation on the second delayed signal and the control signal to generate a second signal.
7 more elements
Dependencies are inferred from the claim text.