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AssigneeIndustrial Technology Research Institute
InventorsYung-Cheng Ma, Tengh-Yih Wang, Hsien-Feng Kuo, Chi-Lung Wang
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An apparatus for switchable conditional execution in a VLIW processor is provided, comprising one or more decoders, one or more ALU with control units, and a register file. The decoder loads and decodes instructions from a fetch unit for decoding and sending the decoded instructions to the ALU with control units for execution. The register file stores and forwards the results on result buses to the decoders. The execution of a VLIW instruction includes a fetch stage, a decode stage, plural execution stages and a write-back stage. The invention has the features of approximate ASIC timing by conditional write-back with the compiler support for the conditional write-back, condition resolved just before write-back, software selective conditional issue and conditional write-back modes, and without hardware interlock/dependence checking for the VLIW processor.
An apparatus for switchable conditional execution (CE) in a very long instruction word (VLIW) processor, said apparatus comprising:
A switchable conditional execution method performed in a very long instruction word (VLIW) processor, said method comprising the steps of:
Dependencies are inferred from the claim text.