Method to detect a stalled instruction stream and serialize micro-operation execution

A computer implemented method for ensuring forward progress of instructions in a pipeline of a processor, the computer implemented method comprising:

• receiving at least one architected instruction in the pipeline, the architected instruction being implemented using a microcode routine that includes a plurality of micro-instructions;
• counting instruction flushes in the pipeline using a counter that is included within a component in a completion unit in the processor to determine a flush count;
• receiving, within the component, a completion signal in response to the architected instruction completing successfully;
• receiving, within the component, a flush signal in response to flushing one of the plurality of micro-instructions;
• outputting, by the component, control signals that are used to control the counter, the control signals being selected using the completion signal and the flush signal;
• responsive to the flush count exceeding a threshold, entering a single step mode in the pipeline;
• responsive to entering the single step mode, executing the plurality of micro-instructions in serial until the architected instruction is complete;
• wherein in single step mode, a next micro-instruction in the microcode routine is not issued for execution until a prior micro-instruction has completed execution;
• and
• responsive to the architected instruction completing, exiting the single step mode in the pipeline and returning to fully pipelined mode.