Network processor system on chip with bridge coupling protocol converting multiprocessor macro core local bus to peripheral interfaces coupled system bus

A System-on-Chip (SoC) protocol converter integrated circuit (IC) comprising:

• an embedded System-on-Chip (SoC) core for protocol conversion, a microprocessor;
• and,
• a local system communications bus, said embedded System-on-Chip (SoC) core for protocol conversion comprising:
• a processor based sub-system including two or more processor cluster assemblies, each processor cluster assembly comprising:
• one or more sub processing cores each capable of performing operations to implement protocol conversion capability;
• a local storage device associated with said one or more sub processing cores in said processor cluster assembly for storing at least one of data and instructions in each processor cluster assembly;
• and,
• a first local interconnect means residing in each said processor cluster assembly for enabling communication of instructions and data between said local storage device and said one or more sub processing cores;
• one or more interface devices enabling receipt and transmission of communications packets according to one or more communications protocols;
• and
• a second local interconnect means residing in said embedded SoC core for enabling communication between either two or more processor clusters and said one or more interface devices or, two or more sub processor cores within a processor cluster and said one or more interface devices;
• and,
• a bridging device for enabling send and receive data communications between said second local interconnect means of said embedded SoC core for protocol conversion and said local system communications bus of said SoC protocol converter IC,
• wherein an interface device is configurable as an inbound network interface adapted for receiving packets generated according to a first protocol type for forwarding to a processor cluster assembly or sub processing core within a processor cluster assembly programmed for processing said packets to implement protocol conversion and, is configurable as an outbound interface device for outputting converted packets of a second protocol type, whereby protocol conversion processing is performed entirely within the SoC integrated circuit chip.