Parallel operation processor utilizing SIMD data transfers

A single instruction multiple data (SIMD) processor comprising a plurality of processing elements, wherein each of the plurality of processing elements includes:

• a transfer pattern storage unit operable to store a transfer pattern value that indicates a processing element from which data is transferred;
• a transfer unit operable to perform a data transfer from the processing element indicated by the transfer pattern value;
• and
• an update unit operable to update the transfer pattern value stored in the transfer pattern storage unit based on a transfer pattern value variation that indicates an amount of variation of the transfer pattern value, wherein
• the transfer unit performs a next data transfer based on the transfer pattern value after the update by the update unit.