Switch memory architectures
AssigneeColorado State University Research Foundation
InventorsSanjay Rajopadhye, Lakshminarayanan Renganarayana, Gautam Gupta
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Abstract
The present invention provides a switch memory architecture (SMA) consisting of: (i) processing elements (PE) (ii) memory banks (MB), and (iii) interconnect switches (ISWITCH). The present invention allows for efficient, potentially unbounded data transfer between two adjacent processes by passing a memory handle and the status registers (memory control information) of the MB. This function may be performed by the ISWITCH.
Claims19
A machine with switch memory architecture comprising:
- a d-dimensional grid of N processing elements (PEs), where d and N are arbitrary integers;
- at least one d-dimensional grid of N memory banks (MBs);
- and
- at least one programmable interconnection switch (ISWITCH) having a (d+1)-dimensional grid of switching elements (SEs) configurable to interconnect the N PEs to N MBs, such that each memory bank (MB) of the N MBs is mapped local to one processing element (PE) of the N PEs, wherein the ISWITCH being reconfigurable to remap the interconnection of N PEs to N MBs such that each memory bank (MB) becomes local to a different PE of the N PEs;
- wherein each SE transfers its state to a neighbor SE to remap the interconnection of N PEs to N MBs in a single clock cycle.
A method for implementing a machine with switch memory architecture, comprising:
- configuring a programmable interconnection switch (ISWITCH) to interconnect a plurality of N processing elements (PEs) in a d-dimensional grid, where d is an arbitrary integer, with a plurality of N memory banks (MBs) organized as at least one d-dimensional grid such that each memory bank (MB) of each of the at least one N MBs is local to only one processing element (PE) of the N PEs at any one time;
- reconfiguring the ISWITCH to rotationally reconnect each MB to a different PE in a single clock cycle;
- wherein the ISWITCH comprises a (d+1) dimensional array of switching elements (SEs);
- and
- wherein each SE transfers its state to a neighbor SE to remap the interconnection of N PEs to N MBs in a single clock cycle.
Dependencies are inferred from the claim text.