Data alignment micro-architecture systems and methods

A method comprising:

• reading data from a memory unit;
• determining whether the data is in big endian form;
• if the data is in big endian form, determining if an offset associated with the data is equal to zero;
• if the offset is equal to zero, directing a first part of the data to a first input of a shifter circuit, the shifter being operable to pass the first part of the data through to its output without shifting;
• if the offset is not equal to zero, directing the first part of the data to a second input of the shifter circuit, and directing a second part of the data to the first input of the shifter circuit;
• if the data is in little endian form, directing the first part of the data to the first input of the shifter circuit, and directing the second part of the data to the second input of the shifter circuit;
• shifting the data on the first and second shifter circuit inputs by an amount derived from the offset;
• and
• writing an output from the shifter circuit to the memory unit.

A system comprising:

• a memory unit, the memory unit having at least two inputs operable to accept addresses of data to be retrieved from the memory unit;
• shift count logic operable to calculate a number of bits by which to shift a block of data, the shift count logic including a delay register and a second memeory unit, the shift count logic being further operable to support speculative execution by storing previous values of delay register data in the second memory unit, and restoring the previous values based on branching information received from a processor;
• mode selection logic operable to indicate whether the block of data is stored in big endian form;
• and
• a shifter communicatively coupled to the memory unit and the shift count logic, the shifter being operable to accept data from the memory unit and to shift it by an amount specified by, or derived from, a value provided by the shift count logic.

A system comprising:

• a memory unit;
• mode selection logic operable to indicate whether a block of data is stored in the memory unit in big endian form;
• shift count logic communicatively coupled to the mode selection logic, the shift count logic being operable to calculate a number of bits by which to shift a block of data retrieved from the memory unit;
• a delay register, the delay register being operable to output data retrieved from the memory unit on a first clock cycle;
• a shifter communicatively coupled to the memory unit and the shift count logic, the shifter being operable to accept (i) delay register data from the delay register, and (ii) memory unit data retrieved from the memory unit on a second clock cycle, and to shift said delay register data and said memory unit data by an amount specified by, or derived from, a value provided by the shift count logic;
• and
• delay register control logic, the delay register control logic being communicatively coupled to the mode selection logic, and being operable to select, for storage in the delay register, a first shifter input or a second shifter input, the selected shifter input holding data retrieved from the memory unit on the second clock cycle.