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US 7,412,579 B2Granted
Secure memory controller
OwnerDennis M. O'Connor, Mark N. Fullerton +1inventors
InventorsDennis M. O'Connor, Mark N. Fullerton, Ray Richardson
Life of this patent
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Abstract
A memory controller partitions memory into secure partitions and non-secure partitions.
Claims8
An integrated circuit comprising:
- a bus master;
- memory to hold instructions having varying levels of security to be executed by the bus master when executing at an appropriate security level;
- and
- a memory controller coupled between the bus master and the memory, the memory controller comprising a memory partitioning mechanism to partition the memory into partitions having one of three or more levels of security wherein the memory partitioning mechanism comprises register sets to define a range of locations within the memory for each security level, and wherein the memory partitioning mechanism is coupled to be responsive to a plurality of signal lines provided on a bus by a bus master to indicate a security level in which the bus master is operating, and to allow execution of instructions in a partition only when the bus master is operating at a security level appropriate for the partition.
1 more element
An integrated circuit comprising:
- a processor;
- a non-volatile memory;
- a first memory controller including a first mechanism to partition the non-volatile memory into partitions with three or more levels of security, the first mechanism comprising register sets to define a range of locations within the memory for each security level;
- a second memory controller including a second mechanism to partition memory external to the integrated circuit into partitions having one of three or more levels of security;
- and
- a bus interconnecting the processor and the first and second memory controllers, the bus including a plurality of signal paths to identify a security status of a memory transaction.
3 more elements
A system comprising:
- an antenna;
- a receiver coupled to the antenna;
- and
- an integrated circuit coupled to the receiver, the integrated circuit including a processor, a non-volatile memory, a first memory controller having a first mechanism to partition the non-volatile memory into partitions having one of three or more levels of security, the first mechanism comprising register sets to define a range of locations within the memory for each security level, a second memory controller including a second mechanism to partition memory external to the integrated circuit into partitions with three or more levels of security, and a bus interconnecting the processor and the first and second memory controllers, the bus including a plurality of signal paths to identify a security status of a memory transaction.
1 more element
Dependencies are inferred from the claim text.