Multiple-location read, single-location write operations using transient blocking synchronization support
AssigneeSun Microsystems, Inc.
InventorsNir N. Shavit, Ori Shalev
Life of this patent
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Abstract
A multiple-location read, single-location write operation is implemented using transient blocking synchronization support. The multiple-location read, single-location write operation involves first acquiring transient ownership of a memory location to be modified and then acquiring transient ownership of at least one other memory location, the contents of which are read and used to modify the memory location first acquired.
Claims22
A computer system, comprising:
- a first processor and a second processor capable of executing processes concurrently;
- and
- a set of memory locations shared by the first processor and the second processor,
- wherein, in response to a request by the first processor to perform a multiple-location read, single-location write synchronization operation, the set of memory locations is restricted from being accessed by the second processor,
- wherein the set of memory locations comprises a memory location to be modified and at least one memory location to be read,
- wherein the memory location to be modified is restricted from being accessed for a first predetermined amount of time and the at least one memory location to be read is restricted from being accessed for a second predetermined amount of time.
A shared-memory multiprocessor computer system having instructions for synchronizing operations on memory, the instructions comprising instructions to:
- request exclusive access to a memory location for a first predetermined amount of time;
- if the request to the memory location is granted, request exclusive access to at least one other memory location for a second predetermined amount of time;
- and
- if the request to the at least one other memory location is granted, modify the memory location dependent on contents of the at least one other memory location.
A method of performing computer system operations, comprising:
- attempting to access a value in a first memory location by a first process in a shared-memory multiprocessor system;
- if the first memory location is accessible, restricting a second process from accessing the first memory location for a first predetermined amount of time;
- attempting to access a value in a second memory location by the first process;
- if the second memory location is accessible, restricting the second process from accessing the second memory location for a second predetermined amount of time;
- and
- during the first predetermined amount of time, modifying the first memory location dependent on contents of the second memory location.
A computer system, comprising:
- a plurality of processors;
- a memory shared by the plurality of processors, the memory comprising a first memory location and a second memory location;
- and
- a controller configured to:
- in response to one of the plurality of processors, request exclusive access to the first memory location for a first predetermined amount of time;
- if the request to the first memory location is granted, request exclusive access to the second memory location for a second predetermined amount of time;
- and
- if the request to the second memory location is granted, modify the first memory location dependent on contents of the second memory location.
Dependencies are inferred from the claim text.