Small and power-efficient cache that can provide data for background DNA devices while the processor is in a low-power state

A system including:

• a microprocessor configured to access a dynamic random access read/write memory (dram);
• a buffer/mini-cache coupled to the microprocessor;
• and
• a direct memory access (dma) device;
• wherein the buffer/mini-cache is configured to pre-fill data from the microprocessor in response to a transition request for the microprocessor to enter a low-power state, wherein the microprocessor is responsive to the transition request after the data is pre-filled, wherein the buffer/mini-cache is enabled to conditionally provide a first portion of the data in response to a read request from the dma device,wherein the buffer/mini-cache is enabled to conditionally modify a second portion of the data in response to a write request from the dma device, wherein the buffer/mini-cache is enabled to flush the second portion of the data to the microprocessor, and wherein the microprocessor is responsive to a transition request for the microprocessor to exit the low-power state after the buffer/mini-cache is flushed.

A method, comprising:

• responding, while a coherency domain is in an incoherent mode, to selected read and write accesses by referencing a buffer/mini-cache;
• pre-filling, before entry to the incoherent mode, at least a portion of the buffer/mini-cache with pre-fill data from the coherency domain;
• and
• before the coherency domain enters a coherent mode, flushing modified information from the buffer/mini-cache to the coherency domain and marking regions of the buffer/mini-cache holding unmodified information as available for pre-filling;
• wherein the responding to one of the selected read accesses includes searching the buffer/mini-cache for read data to satisfy the one of the read accesses, and the responding to one of the selected write accesses includes searching the buffer/mini-cache for a location to store write data provided by the one of the write accesses.