US 7,412,567 B2 · Value-based memory coherence support

Abstract

In one embodiment, a processor comprises a coherence trap unit and a trap logic coupled to the coherence trap unit. The coherence trap unit is also coupled to receive data accessed in response to the processor executing a memory operation. The coherence trap unit is configured to detect that the data matches a designated value indicating that a coherence trap is to be initiated to coherently perform the memory operation. The trap logic is configured to trap to a designated software routine responsive to the coherence trap unit detecting the designated value. In some embodiments, a cache tag in a cache may track whether or not the corresponding cache line has the designated value, and the cache tag may be used to trigger a trap in response to an access to the corresponding cache line.

Claims19

Dependent claims

A processor comprising:

a store queue configured to store addresses to be written in response to stores and store data, and wherein the store queue is coupled to a load data path that delivers load data to a destination of the load, the store queue coupled to the load data path to forward store data for a matching load address;
a coherence trap unit coupled to the load data path prior to a point at which the store data from the store queue is merged with other data to receive memory data accessed in response to the processor executing a load memory operation, wherein the coherence trap unit is configured to detect whether the memory data matches a designated value indicating that a coherence trap is to be initiated to coherently perform the memory operation;
and
trap logic coupled to the coherence trap unit and configured to trap to a designated software routine responsive to the coherence trap unit detecting the designated value.

1 more element

Dependencies are inferred from the claim text.

Value-based memory coherence support

Life of this patent

Value-based memory coherence support

Life of this patent

Abstract

Claims19