US 7,412,566 B2 · Memory hub and access method having internal prefetch buffers

Abstract

A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests which addresses in the memory devices from which date are likely to be subsequently read. The history logic applies prefetch suggestions corresponding to the predicted addresses to a memory sequencer, which uses the prefetch suggestions to generate prefetch requests that are coupled to the memory devices. Data read from the memory devices responsive to the prefetch suggestions are stored in a prefetch buffer. Tag logic stores prefetch addresses corresponding to addresses from which data have been prefetched. The tag logic compares the memory request addresses to the prefetch addresses to determine if the requested read data are stored in the prefetch buffer. If so, the requested data are read from the prefetch buffer. Otherwise, the requested data are read from the memory devices.

Claims73

Dependent claims

A system for prefetching data in a memory system comprising:

a link interface receiving memory requests for access to memory cells in at least one of a plurality of memory devices;
a memory device interface coupled to the memory devices, the memory device interface being operable to transfer memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests;
and
a prefetch circuit coupled to the link interface to receive memory requests from the link interface and coupled to the memory device interface to receive data from the memory cells, the prefetch circuit operable to predict addresses that are likely to be accessed in the memory devices based on the memory requests and to prefetch and store data from memory cells according to the predicted addresses, the prefetch circuit further operable to provide the prefetched data to the link interface responsive to subsequent memory requests, the prefetch circuit being configured to detect a pattern from which addresses to memory requests likely to be accessed are predicted, and to generate prefetch suggestions indicative of addresses corresponding to the predicted memory requests.

1 more element

A system for prefetching data in a memory system comprising:

a link interface receiving memory requests for access to memory cells in at least one of a plurality of memory devices;
a memory device interface coupled to the memory devices, the memory device interface being operable to transfer memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests;
and
a prefetch circuit coupled to the link interface to receive memory requests from the link interface and coupled to the memory device interface to receive data from the memory cells, the prefetch circuit operable to predict addresses that are likely to be accessed in the memory devices based on the memory requests and to prefetch and store data from memory cells according to the predicted addresses, the prefetch circuit further operable to provide the prefetched data to the link interface responsive to subsequent memory requests, the prefetch circuit further comprising:
a plurality of prefetch buffers coupled to the memory device interface for receiving and storing prefetched data from memory cells being accessed based on the predicted addresses;
and
a data read control circuit coupled to the memory device interface, the link interface, and the plurality of prefetch buffers, the data read control circuit operable to determine from the memory requests received from the link interface if the data corresponding to the memory requests are stored in the plurality of prefetch buffers, the data read control circuit further operable to transfer data from the plurality of prefetch buffers if the requested data are stored in the plurality of prefetch buffers and to transfer data from the memory device interface if the data are stored in the memory cells.

4 more elements

A memory hub comprising:

a link interface receiving memory requests for access to memory cells in at least one of a plurality of memory device;
a memory device interface coupled to the memory devices, the memory device interface being operable to transfer memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive data responsive to at least some of the memory requests;
a prefetch circuit coupled to the link interface to receive memory requests from the link interface and coupled to the memory device interface to receive data from the memory cells, the prefetch circuit operable to predict addresses that are likely to be accessed in the memory devices based on the memory requests and generate prefetch suggestions indicative of the predicted addresses to prefetch data from memory cells, the prefetch circuit further operable to store the data that are prefetched and transfer the prefetch data to the link interface;
and
a memory sequencer coupled to the link interface, the memory device interface and the prefetch circuit, the memory sequencer operable to transfer memory requests received from the link interface to the prefetch circuit to determine if the data corresponding to the memory requests are stored in the prefetch circuit, the memory sequencer further being operable to transfer memory requests received from the link interface to the memory device interface to fetch the data corresponding to the memory requests if the data are not stored in the prefetch circuit, the memory sequencer further being operable to generate prefetch requests responsive to the prefetch suggestions received from the prefetch circuit to fetch data corresponding to the prefetch suggestions.

2 more elements

A computer system, comprising:

a central processing unit (“CPU”);
a system controller coupled to the CPU, the system controller having an input port and an output port;
an input device coupled to the CPU through the system controller;
an output device coupled to the CPU through the system controller;
a storage device coupled to the CPU through the system controller;
a plurality of memory modules, each of the memory modules comprising:
a plurality of memory devices;
and
a system for prefetching data comprising:
a link interface receiving memory requests for access to memory cells in at least one of the memory devices;
a memory device interface coupled to the memory devices, the memory device interface being operable to transfer memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests;
and
a prefetch circuit coupled to the link interface to receive memory requests from the link interface and coupled to the memory device interface to receive data from the memory cells, the prefetch circuit operable to predict addresses that are likely to be accessed in the memory devices based on the memory requests and to prefetch and store data from memory cells according to the predicted addresses, the prefetch circuit further operable to provide the prefetched data to the link interface responsive to subsequent memory requests, the prefetch circuit being configured to detect a pattern from which addresses to memory requests likely to be accessed are predicted, and operable to generate prefetch suggestions indicative of addresses corresponding to the predicted memory requests.

10 more elements

A computer system, comprising:

a central processing unit (“CPU”);
a system controller coupled to the CPU, the system controller having an input port and an output port;
an input device coupled to the CPU through the system controller;
an output device coupled to the CPU through the system controller;
a storage device coupled to the CPU through the system controller;
a plurality of memory modules, each of the memory modules comprising:
a plurality of memory devices;
and
a memory hub comprising:
a link interface receiving memory requests for access to memory cells in at least one of the memory devices;
a memory device interface coupled to the memory devices, the memory device interface being operable to transfer memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive data responsive to at least some of the memory requests;
a prefetch circuit coupled to the link interface to receive memory requests from the link interface and coupled to the memory device interface to receive data from the memory cells, the prefetch circuit operable to predict addresses that are likely to be accessed in the memory devices based on the memory requests and generate prefetch suggestions indicative of the predicted addresses to prefetch data from memory cells, the prefetch circuit further operable to store the data that are prefetched and transfer the prefetched data to the link interface;
and
a memory sequencer coupled to the link interface, the memory device interface and the prefetch circuit, the memory sequencer operable to transfer memory requests received from the link interface to the prefetch circuit to determine if the data corresponding to the memory requests are stored in the prefetch circuit, the memory sequencer further being operable to transfer memory requests received from the link interface to the memory device interface to fetch the data corresponding to the memory requests if the data are not stored, in the prefetch circuits, the memory sequencer further operable to generate prefetch requests responsive to the prefetch suggestions received from the prefetch circuit to fetch data corresponding to the prefetch suggestions.

11 more elements

A computer system, comprising:

a central processing unit (“CPU”);
a system controller coupled to the CPU, the system controller having an input port and an output port;
an input device coupled to the CPU through the system controller;
an output device coupled to the CPU through the system controller;
a storage device coupled to the CPU through the system controller;
a plurality of memory modules, each of the memory modules comprising:
a plurality of memory devices;
and
a system for prefetching data comprising:
a link interface receiving memory requests for access to memory cells in at least one of the memory devices;
a memory device interface coupled to the memory devices, the memory device interface being operable to transfer memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests;
and
a prefetch circuit coupled to the link interface to receive memory requests from the link interface and coupled to the memory device interface to receive data from the memory cells, the prefetch circuit operable to predict addresses that are likely to be accessed in the memory devices based on the memory requests and to prefetch and store data from memory cells according to the predicted addresses, the prefetch circuit further operable to provide the prefetched data to the link interface responsive to subsequent memory requests, the prefetch circuit further comprising:
a plurality of prefetch buffers coupled to the memory device interface for receiving and storing prefetched data from memory cells being accessed based on the predicted addresses;
and
a data read control circuit coupled to the, memory device interface, the link interface, and the plurality of prefetch buffers, the data read control circuit operable to determine from the memory requests received from the link interface if the data corresponding to the memory requests are stored in the plurality of prefetch buffers, the data read control circuit further operable to transfer data from the plurality of prefetch buffers if the requested data are stored in the plurality of prefetch buffers and to transfer data from the memory device interface if the data are stored in the memory cells.

13 more elements

A method of reading data in a memory hub comprising:

receiving memory requests for access to a memory device;
coupling the memory requests to the memory device responsive to the received memory request, at least some of the memory requests being memory requests to read data;
receiving read data responsive to the read memory requests;
predicting addresses that are likely to be accessed in the memory device based on the read memory requests;
generating prefetch requests indicative of the predicted addresses;
prefetching and storing the read data from the memory device responsive to the prefetch requests;
determining from a read memory request if the requested read data are stored as prefetched data;
transferring the prefetched data if a determination has been made;
transferring data from the memory device if a determination has not been made;
grouping the predicted addresses into a plurality of sets corresponding to respective strides;
dividing the stored prefetched data into a plurality of sections each corresponding to a respective stride;
and
storing the prefetched data from the memory devices indicative of the predicted addresses in the section corresponding to the stride containing the predicted address from which the data was read.

10 more elements

Dependencies are inferred from the claim text.

Memory hub and access method having internal prefetch buffers

Life of this patent

Memory hub and access method having internal prefetch buffers

Life of this patent

Abstract

Claims73