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US 7,412,561 B2Granted
Transposing of bits in input data to form a comparand within a content addressable memory
AssigneeNetLogic Microsystems, Inc.
InventorsDimitri C. Argyres, Varadarajan Srinivasan
Life of this patent
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Abstract
An apparatus and method of transposing one or more bits in input data relative to other bits of the input data to form a compound for searching in a content addressable memory. The comparand may have one or more bits rearranged from their order appearing in the input data such that one or more bits from a first segment of the input data are replaced with, or substituted by, one or more bits from a second segment of the input data.
Claims22
An apparatus, comprising:
- control logic comprising a plurality of logic cells, at least one of the plurality of logic cells configured to receive an A operand and a B operand and perform the following logic operations comprising ĀB, A B, and AB;
- and
- switch circuitry coupled to receive input data, the switch circuitry coupled to the control logic to receive a result of the AB logic operation from each of the plurality of logic cells and selectively enable the output of one or more bits of the input data based on the results of the AB logic operations;
- wherein the control logic is coupled to receive a first plurality of enable signals, each of the first plurality of enable signals corresponding to a first plurality of one or more bits of a first segment of the input data, and wherein the control logic is coupled to receive a second plurality of enable signals, each of the second plurality of enable signals corresponding to a second plurality of one or more bits of a second segment of the input data.
1 more element
An apparatus, comprising:
- control logic comprising a plurality of logic cells, at least one of the plurality of logic cells configured to receive an A operand and a B operand and perform the following logic operations comprising ĀB. A B, and AB;
- and
- switch circuitry coupled to receive input data, the switch circuitry coupled to the control logic to receive a result of the AB logic operation from each of the plurality of logic cells and selectively enable the output of one or more bits of the input data based on the results of the AB logic operations;
- a content addressable memory (CAM) array coupled to receive a comparand;
- and
- a filter circuit coupled to the CAM array, the filter circuit comprising the switch circuitry and the control logic, wherein the filter circuit is coupled to receive the input data and transpose the one or more bits of the input data from an initial position in the input data to a different position in the comparand relative to other bits of the input data that are transposed to the comparand.
3 more elements
An apparatus, comprising:
- control logic comprising a plurality of logic cells, at least one of the plurality of logic cells configured to receive an A operand and a B operand and perform the following logic operations comprising ĀB, A B, and AB;
- and
- switch circuitry coupled to receive input data, the switch circuitry coupled to the control logic to receive a result of the AB logic operation from each of the plurality of logic cells and selectively enable the output of one or more bits of the input data based on the results of the AB logic operations;
- wherein at least another of the plurality of logic cells is configured to receive a result of the ĀB logic operation of the at least one logic cell and an enable signal as the B operand, and wherein the at least another of the plurality of logic cells is configured to perform the AB logic operation.
1 more element
A method, comprising:
- providing a matrix of M rows and N columns of logic cells in a content addressable memory (CAM) device, where N is equal to or greater than 1 and M is greater than 1;
- performing an AB logic operation in each of the logic cells;
- selecting among a second one or more bits of input data using a result of the AB logic operation in at least one of the logic cells;
- and
- selecting between the selected second one or more bits of input data and a first one or more bits of input data for output to a comparand in the CAM device.
2 more elements
A content addressable memory (CAM) device, comprising:
- a matrix of M rows and N columns of logic cells, where N is equal to or greater than 1 and M is greater than 1;
- means for performing an AB logic operation in each of the logic cells;
- means for selecting among a second one or more bits of input data using a result of the AB logic operation in at least one of the logic cells;
- and
- means for selecting between the selected second one or more bits of input data and a first one or more bits of input data for output to a comparand in the CAM device.
2 more elements
Dependencies are inferred from the claim text.