Back to results
US 7,412,471 B2Granted
Discrete filter having a tap selection circuit
AssigneeIntel Corporation
InventorTinku Acharya
Life of this patent
Estimating the term…
Abstract
A digital signal processing circuit includes a chain of processing units having a selectable number of taps and a tap selection circuit. The tap selection circuit is coupled to the chain of processing units to establish the number of taps of the chains.
Claims17
A digital signal processing circuit comprising:
- a processing chain having a selectable number of taps and progressively accumulating a sum along the taps, the processing chain comprising a serial chain of processing units and each of the processing units having a different gain;
- and
- a tap selection circuit coupled to the processing chain to selectively establish the number of taps of the chain, the tap selection circuit comprising a multiplexer to select one of the taps as the beginning tap in the chain and set an accumulated sum at the selected tap to zero.
A method comprising:
- providing a processing chain line having a fixed number of taps;
- disabling some of the taps of the chain comprising selecting one of the taps as the beginning tap in the delay line and setting an accumulated sum at the selected tap to zero;
- and
- using the remaining taps to establish a finite impulse response filter.
1 more element
A system comprising:
- a filter comprising:
- a processing chain having a selectable number of taps and progressively accumulating a sum along the taps the processing chain comprising a serial chain of processing units and each of the processing units having a different gain;
- a tap selection circuit coupled to the processing chain to selectively establish the number of taps of the chain, the tap selection circuit comprising a multiplexer to select one of the taps as the beginning tap in the chain and set an accumulated sum at the selected tap to zero;
- and
- a processor coupled to the filter.
2 more elements
Dependencies are inferred from the claim text.