PN code generator, GOLD code generator, PN code despreader, method for generating PN code, method for generating GOLD code, method for despreading PN code and computer program

A GOLD code generator, comprising:

• two PN code generators;
• and
• an exclusive OR operation circuit taking an exclusive OR of two PN codes generated by said two PN code generators,
• wherein said PN code generator including:
• a code memory storing shift code patterns at continuous partial phases among the shift code patterns at plural phases which are given to the respective flip-flops when a linear feedback shift register is operated;
• a code mask memory storing mask code patterns, which are partial mask code patterns among the plural mask code patterns to shift a phase of a PN code to be generated, and which shift the phase of the PN code to be generated by a multiple of a stored number of the shift code patterns at the continuous partial phases;
• a logical AND operation circuit generating a new code pattern by taking a logical AND of bits in the same order of the shift code pattern stored in said code memory and the mask code pattern stored in said code mask memory;
• and
• a second exclusive OR operation circuit generating the PN code by taking an exclusive OR of the new code pattern generated by said logical AND operation circuit.

A GOLD code generator, comprising:

• a code memory storing shift code patterns at continuous partial phases among the shift code patterns at plural phases which are given to the respective flip-flops when a liner feedback shift register is operated;
• a code mask memory storing mask code patterns, which are partial mask code patterns among the plural mask code patterns to shift a phase of a PN code to be generated, and which shift the phase of the PN code to be generated by a multiple of a stored number of the shift code patterns at the continuous partial phases;
• a first and second logical AND circuits generating two new code patterns by taking a logical AND of bits in the same order of the shift code pattern stored in said code memory and the mask code pattern stored in said code mask memory;
• a first and second exclusive OR operation circuits generating two PN codes by taking an exclusive OR of the respective two new code patterns generated by said first and second logical AND operation circuits;
• a third exclusive OR operation circuit to take the exclusive OR of the two PN codes generated by said first and second exclusive OR operation circuits;
• and
• a control circuit to control the shift code pattern stored in said code memory and the mask code pattern stored in said code mask memory to be outputted to said first and second logical AND operation circuits by time sharing.

A PN code despreader, comprising:

• a PN code generator generating a PN code;
• and
• an exclusive OR operation circuit despreading a received data by taking an exclusive OR between the PN code generated from the PN code generator and the received data;
• and
• wherein said PN code generator including:
• a code memory storing shift code patterns at continuous partial phases among the shift code patterns at plural phases which are given to the respective flip-flops when a liner feedback shift register is operated;
• a code mask memory storing mask code patterns, which are partial mask code patterns among the plural mask code patterns to shift a phase of a PN code to be generated, and which shift the phase of the PN code to be generated by a multiple of a stored number of the shift code patterns at the continuous partial phases;
• a logical AND operation circuit generating a new code pattern by taking a logical AND of bits in the same order of the shift code pattern stored in the code memory and the mask code pattern stored in the code mask memory;
• and
• a second exclusive OR operation circuit generating the PN code by taking the exclusive OR of the new code pattern generated by the logical AND operation circuit.

A PN code despreader, comprising:

• a buffer storing a received data temporary;
• a PN code generator generating plural PN codes at the same time;
• and
• a Matched filter despreading the plural PN code generated by said PN code generator and the received data having the same number of bits with the generated PN code,
• wherein said PN code generator includes:
• a code memory storing shift code patterns at continuous partial phases among the shift code patterns at plural phases which are given to the respective flip-flops when a liner feedback shift register is operated;
• a code mask memory storing mask code patterns, which are partial mask code patterns among the plural mask code patterns to shift a phase of a PN code to be generated, and which shift the phase of the PN code to be generated by a multiple of a stored number of the shift code patterns at the continuous partial phases, and to store the mask code pattern at least at one phase following to the above-described phase of the mask code pattern;
• and
• plural phase shift circuits generating the plural PN codes by using the mask code patterns at the continuous phases stored in said code mask memory and the shift code patterns stored in said code memory,
• wherein said phase shift circuit includes:
• a logical AND operation circuit generating a new code pattern by taking a logical AND of bits in the same order of the shift code pattern stored in said code memory and the mask code pattern stored in said code mask memory;
• and
• an exclusive OR operation circuit generating the PN code by taking an exclusive OR of the new code pattern generated by the logical AND operation circuit.

A PN code generator generating a PN code at a random phase, comprising:

• a code memory storing a shift code pattern corresponding to a partial phase of the PN code;
• a code mask memory storing a mask code pattern corresponding to a phase shift of a partial phase shift amount of the PN code;
• and
• an operation circuit selecting the required shift code patterns from among the shift code patterns corresponding to the partial phases stored in the code memory, and selecting the required mask code patterns from among the mask code patterns of a random phase shift amount corresponding to the partial phases stored in the code mask memory, and thereby, generating the PN code at a random phase by a combination of the selected shift code patterns and the selected mask code patterns from the phase of the PN code to be generated.