Control signal training

A memory module, comprising:

• a memory array including a plurality of memory cells;
• a memory controller configured for transmitting control signals, data signals and sampling clock signals;
• a control signal latch configured for latching control signals in relation to the sampling clock signals;
• a bidirectional data signal transmission bus connected to the memory array and the memory controller, the bidirectional data signal transmission bus configured for transmitting data signals between the memory array and the memory controller;
• an control signal transmission bus connected to the memory controller and the control signal latch, the control signal transmission bus configured for transmitting control signals from the memory controller to the control signal latch;
• a sampling clock signal transmission line connected to the memory controller and the control signal latch, the sampling clock signal transmission line configured for transmitting sampling clock signals from the memory controller to the control signal latch;
• a control unit configured for setting a training mode, and
• a multiplexer connected to the control signal latch, the control unit and to the bidirectional data signal transmission bus, the multiplexer being configured to read out the control signals latched in the control signal latch to the memory controller in the training mode;
• wherein in the training mode the memory controller is configured for determining concordance of the control signals outputted by the memory controller and the control signals read out by the multiplexer from the control signal latch, the memory controller further configured for adapting the time phase between the control signals and the sampling clock signals step-by-step until concordance of the control signals outputted by the memory controller and the control signals read out the multiplexer from the control signal latch is determined by the memory controller.

A computer system, comprising:

• a signal transmitting unit configured for outputting control signals and sampling clock signals, the control signals and the sampling clock signals;
• a signal receiving unit configured for latching control signals in relation to the sampling clock signals;
• a control signal transmission bus connected to the signal transmitting unit and the signal receiving unit, the control signal transmission bus configured for transmitting control signals from the signal transmitting unit to the signal receiving unit;
• a sampling clock signal transmission line connected to the signal transmitting unit and the signal receiving unit, the sampling clock signal transmission line configured for transmitting sampling clock signals from the signal transmitting unit to the signal receiving unit;
• a reading unit connected to the signal receiving unit, the reading unit configured for reading the control signals latched in the control signal receiving unit;
• and
• an evaluation unit connected to the reading unit and the signal transmitting unit, the evaluation unit configured for determining concordance of the control signals outputted by the signal transmitting unit and the control signals read out by the reading unit from the signal receiving unit, the evaluation unit further configured for calibrating the time phase between the control signals and the sampling clock signals until concordance of the control signals outputted by the signal transmitting unit and the control signals read out the reading unit from the signal receiving unit is determined by the evaluation unit.

A computer system, comprising:

• a plurality of storage units configured for transmitting data signals via a bidirectional data signal transmission bus to the plurality of storage units;
• a signal transmitting unit configured for outputting control signals and sampling clock signals, the control signals and the sampling clock signals;
• a signal receiving unit configured for latching control signals in relation to the sampling clock signals;
• a control signal transmission bus connected to the signal transmitting unit and the signal receiving unit, the control signal transmission bus configured for transmitting control signals from the signal transmitting unit to the signal receiving unit;
• a sampling clock signal transmission line connected to the signal transmitting unit and the signal receiving unit, the sampling clock signal transmission line configured for transmitting sampling clock signals from the signal transmitting unit to the signal receiving unit;
• a reading unit connected to the signal receiving unit and the bidirectional data signal transmission bus, the reading unit configured for reading the control signals latched in the control signal receiving unit and further configured for outputting the control signals to the bidirectional data signal transmission bus;
• and
• an evaluation unit connected to the reading unit via the bidirectional data signal transmission bus and the signal transmitting unit, the evaluation unit configured for determining concordance of the control signals outputted by the signal transmitting unit and the control signals read out by the reading unit from the signal receiving unit, the evaluation unit further configured for calibrating the time phase between the control signals and the sampling clock signals until concordance of the control signals outputted by the signal transmitting unit and the control signals read out the reading unit from the signal receiving unit is determined by the evaluation unit.

A control signal training method for an integrated circuit latching control signals in relation to sampling clock signals, the control signal training method comprising a training loop of:

• launching an control signal and a sampling clock signal;
• latching the control signal in relation to the sampling clock signal;
• retransmitting the latched control signal;
• and
• determining concordance of the launched control signal and the latched control signal;
• wherein, if an control signal match is determined, the training loop is terminated;
• and
• wherein, if an control signal mismatch is determined, the time phase between the control signal and the sampling clock signal is shifted and the training loop is repeated.