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US 7,411,857 B2Granted
Power savings in active standby mode
AssigneeMicron Technology, Inc.
InventorScott Schaefer
Life of this patent
Estimating the term…
Abstract
Apparatus for reducing the power consumed by a memory device selectively activates a power saving mode in which operation of a delay compensation circuit may be suspended during an active power down mode of operation.
Claims17
A computer system, comprising:
- a processor;
- and
- a memory device coupled to the processor, wherein the memory device comprises:
- a circuit to enable selection of a first power saving mode of operation for the memory device, the first power savings mode comprising exiting an active power-down mode of operation of the memory device in more than one clock cycle.
1 more element
A computer system, comprising:
- a processor;
- and
- a memory device coupled to the processor, wherein the memory device comprises:
- a circuit to enable selection of a first power saving mode of operation for the memory device, the first power savings mode comprising exiting an active power-down mode of operation of the memory device in two clock cycles;
- wherein the memory device is configured to enable selection of a second power saving mode to permit exiting the active power-down mode of operation in only one clock cycle.
2 more elements
A memory device, comprising:
- a controller for controlling operations of the memory device, wherein the controller is adapted to permit transitioning from an active power-down mode of operation of the memory device to a normal mode of operation by suspending operation of a delay compensation circuit during the active power-down mode of operation and providing more than one clock cycle to exit the power-down mode of operation.
A memory device, comprising:
- a controller for controlling operations of the memory device, wherein the controller is adapted to permit transitioning from an active power-down mode of operation of the memory device to a normal mode of operation by suspending operation of a delay compensation circuit during the active power-down mode of operation and providing more than one clock cycle to exit the power-down mode of operation;
- wherein the controller is further adapted to permit exiting the active power-down mode of operation in only one clock cycle.
A memory device, comprising:
- a controller for controlling operations of the memory device, wherein the controller is adapted to perform two modes of operation for enabling the conservation of power in a power-down mode of operation of the memory device, wherein the modes comprise:
- a first active power-down mode of operation, wherein suspending operation of a delay locked loop during the first active power-down mode of operation is permitted by allowing more than one clock cycle to exit the first active power-down mode of operation;
- and
- a second active power-down mode of operation, wherein suspending operation of the delay locked loop during the second active power-down mode of operation is not permitted by allowing only one clock cycle to exit the second active power-down mode of operation.
1 more element
A memory device, comprising:
- a controller for controlling operations of the memory device, wherein the controller is adapted to perform two modes of operation for enabling the conservation of power in a power-down mode of operation of the memory device, wherein the modes comprise:
- a first active power-down mode of operation, wherein suspending operation of a delay locked loop during the first active power-down mode of operation is permitted by allowing more than one clock cycle to exit the first active power-down mode of operation;
- and
- a second active power-down mode of operation, wherein suspending operation of the delay locked loop during the second active power-down mode of operation is not permitted by allowing only one clock cycle to exit the second active power-down mode of operation;
- wherein the second active power-down mode of operation is in compliance with an industry wide standard;
- and
- wherein one of the first or second active power-down modes of operation is selected by programming a register.
4 more elements
Dependencies are inferred from the claim text.