Volatile memory elements with elevated power supply levels for programmable logic device integrated circuits

A programmable logic device integrated circuit comprising:

• a region of programmable core logic including transistors, wherein the core logic is powered at a core logic power supply level;
• and
• an array of volatile memory elements powered with a memory element power supply level that is greater than the core logic power supply level, wherein the memory elements are loaded with configuration data and provide corresponding output signals that are applied to respective gates of the transistors, wherein the core logic power supply level is provided using a core logic positive power supply voltage and a core logic ground and wherein the memory element power supply level is provided using a memory element positive power supply voltage and a memory element ground, wherein when the output signals are being provided to the respective gates of the transistors, the memory elements are being powered using a memory element positive power supply voltage that is greater than the core logic positive power supply voltage and using a memory element ground power supply voltage that is less than the core logic ground power supply voltage, wherein each memory element comprises an address transistor controlled by an address line with associated address signals, and wherein the associated address signals have logic high levels equal to the memory element positive power supply voltage and logic low levels equal to the memory element ground power supply voltage.

A programmable logic device integrated circuit comprising:

• a region of programmable core logic including transistors, wherein the core logic is powered at a core logic power supply level;
• and
• an array of volatile memory elements powered with a memory element power supply level that is greater than the core logic power supply level, wherein the memory elements are loaded with configuration data and provide corresponding output signals that are applied to respective gates of the transistors, wherein the core logic power supply level is provided using a core logic positive power supply voltage and a core logic ground and wherein the memory element power supply level is provided using a memory element positive power supply voltage and a memory element ground, wherein when the output signals are being provided to the respective gates of the transistors, the memory elements are being powered using a memory element positive power supply voltage that is greater than the core logic positive power supply voltage and using a memory element ground power supply voltage that is less than the core logic ground power supply voltage, wherein each memory element comprises a clear transistor controlled by a clear line with associated clear signals, and wherein the associated clear signals have logic high levels equal to the memory element positive power supply voltage and logic low levels equal to the memory element ground power supply voltage.

A method for using volatile memory elements on a programmable logic device integrated circuit that contains programmable core logic, comprising:

• powering the programmable core logic at a core power supply level;
• powering the volatile memory elements with a memory element power supply level that is elevated with respect to the core power supply level, wherein powering the programmable core logic with the core power supply level comprises powering the programmable core logic using a core logic positive power supply voltage and a core logic ground power supply voltage, wherein powering the memory elements with the memory element power supply level comprises powering the memory elements using a memory element positive power supply voltage and a memory element ground power supply voltage, wherein the memory element positive power supply voltage is greater than the core logic positive power supply voltage, wherein the memory element ground power supply voltage is less than the core logic ground power supply voltage, and wherein each memory element has an n-channel metal-oxide-semiconductor address transistor controlled by an address line;
• and
• asserting and deasserting the address line to load data into the memory elements, wherein asserting the address line comprises raising the address line to the memory element positive power supply voltage and wherein deasserting the address line comprises lowering the address line to the memory element ground power supply voltage.