Semiconductor storage device

A semiconductor storage device comprising:

• information memory cells;
• memory cell arrays including the information memory cells arranged in a matrix;
• information word lines connected to the information memory cells in rows of the memory cell arrays;
• sub bit lines connected to the information memory cells in columns of the memory cell arrays;
• main bit lines connected to the sub bit lines;
• a select transistor connecting one of the sub bit lines to one of the main bit lines;
• reference memory cells provided for the sub bit lines;
• reference word lines connected to the reference memory cells storing one of digital data “0” or “1” and not connected to a reference memory cell storing the other digital data “0” or “1”;
• and
• sense amplifiers connected to two main bit lines included respectively in two memory cell arrays adjacent to each other, one of the sense amplifiers being connected to one of the information memory cells included in one of the two memory cell arrays via one of the two main bit lines and being connected to the reference memory cell included in other memory cell array via the other main bit line when a data is read out from one of the information memory cells, the sense amplifiers using a reference voltage generated by using only the single kind of digital data among digital data “0” and “1”, the reference voltage having a middle potential between a potential of a bit line transmitting data “0” and a potential of a bit line transmitting data “1”;
• first select transistors connected between the information bit lines and the sense amplifiers;
• a second select transistor connected between the reference bit line and the sense amplifiers;
• first load current transistors connecting a power source to the information bit lines;
• and
• a second load current transistor connecting the power source to the reference bit line.