Semiconductor memory arrangement with branched control and address bus

A data memory system, comprising:

• a plurality of semiconductor memory arrangements, individual ones of the semiconductor memory arrangements comprising:
• at least one semiconductor memory chip for the storage of user data;
• a memory controller for control of the at least one semiconductor memory chip;
• and
• at least one unidirectional signal line bus for control and address signals connected with the memory controller and branching at least once, the at least once branching bus directly connecting at least one semiconductor memory chip with the memory controller and connecting the semiconductor memory chips among each other.