Back to results
US 7,411,842 B2Granted
Data arrangement control signal generator for use in semiconductor memory device
AssigneeHynix Semiconductor Inc.
InventorBeom-Ju Shin
Life of this patent
Estimating the term…
Abstract
A data arrangement control signal generation circuit for use in a semiconductor memory device includes a plurality of data arrangement control signal generation units connected in series, each for selectively generating a data arrangement control signal according to a column address strobe (CAS) latency.
Claims21
A data arrangement control signal generation circuit for use in a semiconductor memory device, comprising:
- a plurality of data arrangement control signal generation units connected in series for selectively generating a data arrangement control signal according to a CAS pulse (CASP) signal or a CAS Latency signal based on column address strobe (CAS) latency information and an output of a delay locked loop (DLL),
- wherein a first data arrangement control signal generation unit logically combines the CASP signal enabled based on an external read command and a predetermined address to output a first data arrangement control signal;
- a second data arrangement control signal generation unit transfers the first data arrangement control signal in response to a rising clock that is outputted from the DLL to output a second data arrangement control signal;
- and
- a third data arrangement control signal generation unit selectively transfers the first or second data arrangement control signal in response to a first CAS latency signal and the rising clock, the first CAS latency signal having a first CAS latency information including a first CAS latency value to output a third data arrangement control signal;
- and
- a fourth data arrangement control signal generation unit selectively transfers the third data arrangement control signal in response to the first CAS latency signal, a second CAS latency signal and a falling clock that is outputted from the DLL, the second CAS latency signal having a second CAS latency information including a second CAS latency value to output a fourth data arrangement control signal.
4 more elements
A method for arranging data signals, the method comprising:
- outputting a first data arrangement control signal by logically combining a CASP signal that is enabled with an external read command, and a predetermined address signal;
- transferring the first data arrangement control signal that is inputted under control of a rising clock that is outputted from a delay locked loop, as a second data arrangement control signal;
- selectively transferring the second data arrangement control signal in response to a first CAS latency signal having a first CAS latency information, and the rising clock to output a third data arrangement control signal;
- and
- selectively transferring the third data arrangement control signal in response to the first CAS latency signal, a second CAS latency signal having a second CAS latency information, and a falling clock that is outputted from the delay locked loop.
2 more elements
A data arrangement control signal generation circuit for use in a semiconductor memory device, comprising:
- a first data arrangement control signal generation unit for generating a first data arrangement control signal in response to a CAS pulse (CASP) signal and a DLL clock that is outputted from a delay locked loop (DLL);
- and
- a second data arrangement control signal generation unit for selectively generating a second data arrangement control signal in response to a first CAS Latency signal and the DLL clock
- wherein the first CAS Latency signal has a first CAS latency information corresponding to a first CAS latency value.
1 more element
Dependencies are inferred from the claim text.