Memory having storage means
AssigneeSanyo Electric Co., Ltd.
InventorNaofumi Sakai
Life of this patent
Estimating the term…
Abstract
A memory capable of inhibiting a non-selected cell from disturbance is provided. This memory comprises a bit line, a word line arranged to intersect with the bit line and first storage means connected between the bit line and the word line, for applying voltages of opposite directions to the first storage means of a non-selected memory cell by the same number of times or substantially applying no voltages throughout a read operation and a rewrite operation while varying a rewriting method with a case of reading first data by the read operation and with a case of reading second data by the read operation.
Claims18
A memory comprising:
- a bit line;
- a word line arranged to intersect with said bit line;
- a first storage elements comprising a ferroelectric capacitor connected between said bit line and said word line;
- and
- driving circuitry configured for applying to said first storage element a voltage pulse not inverting storage data of said first storage element simultaneously with, before or after at least one operation of a read operation, a rewrite operation or a write operation.
A memory comprising:
- a bit line;
- a word line arranged to intersect with said bit line;
- a first storage element comprising a ferroelectric capacitor connected between said bit line and said word line;
- and
- driving circuitry configured for applying to said first storage element a first voltage pulse providing an electric field of a first direction inverting storage data of said first storage element and a second voltage pulse providing an electric field opposite to said first direction not inverting storage data of said first storage element in at least one operation of a read operation, a rewrite operation or a write operation.
A memory comprising:
- a bit line;
- a word line arranged to intersect with said bit line;
- a first storage element connected between said bit line and said word line;
- and
- driving circuitry configured for applying to said first storage element a first voltage pulse providing an electric field of a first direction inverting storage data in said first storage element and a second voltage pulse providing an electric field opposite to said first direction not inverting storage data in said first storage element in at least one operation of a read operation or a rewrite operation.
A memory comprising:
- bit lines;
- word lines arranged to intersect with said bit lines, repectively;
- first storage elements each connected between a corresponding bit line and a corresponding word line;
- and
- a driving circuit for driving said bit lines and said word lines, wherein
- said first storage elements include at least a selected first storage element connected to a selected bit line and a selected word line, and an non-selected first storage element other than said selected first storage element, and
- said driving circuit performs a read operation or a rewrite operation to said selected first storage element while applying to said non-selected first storage element a voltage pulse not inverting storage data in said non-selected first storage element in said rewrite operation after said read operation.
Dependencies are inferred from the claim text.