Semiconductor memory device
AssigneeNEC Electronics Corporation
InventorKohji Kanamori
Life of this patent
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Abstract
A drive circuit 22 controls voltages applied to a substrate 1, selection gates SG0 and SG1, a local bit line LB2, and a control gate CGn. By respectively applying a negative voltage to the control gate CGn, a positive voltage to the selection gate SG0, a voltage lower than the voltage applied to the selection gate SG0 to the selection gate SG1, and a positive voltage to the local bit line LB2, the drive circuit 22 controls so that electrons are selectively drawn out of a floating gate FG3 to the local bit line LB2 by F-N tunneling during writing operation. Sufficient operation margin is obtained even when memory cells are miniaturized.
Claims20
A semiconductor memory device comprising:
- a first selection gate disposed in a first region on a substrate;
- a first storage node disposed in a second region adjacent to said first region;
- a local bit line disposed in a third region adjacent to said second region;
- a second storage node disposed in a fourth region adjacent to said third region;
- a second selection gate disposed in a fifth region adjacent to said fourth region on said substrate;
- a control gate disposed on said first storage node and said second storage node;
- and
- a drive circuit that controls voltages applied to said substrate, said first selection gate, said local bit line, said second selection gate, and said control gate;
- wherein
- said drive circuit performs a first control to selectively draw electrons out of said first storage node to said local bit line through F-N tunneling by respectively applying a negative voltage to said control gate, a positive voltage to said second selection gate, a voltage lower than the voltage applied to said second selection gate to said first selection gate, and a positive voltage to said local bit line during a writing operation.
A semiconductor memory device comprising:
- a first selection gate disposed in a first region on a substrate;
- a first storage node disposed in a second region adjacent to said first region;
- a local bit line disposed in a third region adjacent to said second region;
- a second storage node disposed in a fourth region adjacent to said third region;
- a second selection gate disposed in a fifth region adjacent to said fourth region on said substrate;
- a control gate disposed on said first storage node and said second storage node;
- and
- a drive circuit that controls voltages applied to said substrate, said first selection gate, said local bit line, said second selection gate, and said control gate;
- wherein
- said drive circuit comprises:
- means for controlling to respectively apply a negative voltage to said control gate, a positive voltage to said second selection gate, a voltage lower than the voltage applied to said second selection gate to said first selection gate, and a positive voltage to said local bit line during a writing operation, thereby performing a first control to selectively draw electrons out of said first storage node to said local bit line.
Dependencies are inferred from the claim text.