Programming a non-volatile memory device

A method for programming a non-volatile memory array having a plurality of memory cells arranged in columns and rows, each row coupled by a different word line of a plurality of word lines, a lowest word line being closest to an array source line and a highest word line being closest to an array drain line, the method comprising:

• biasing a first word line with a programming voltage to program a first cell;
• performing a verify operation on the first cell;
• and
• incrementing the programming voltage by a step voltage if the verify operation determines the first cell is erased wherein the step voltage increases for each word line from the lowest word line to the highest word line.

A method for programming a non-volatile memory array having a plurality of memory cells arranged in columns and rows, each row coupled by a different word line of a plurality of word lines, a lowest word line being closest to an array source line and a highest word line being closest to an array drain line, the method comprising:

• biasing a first word line with a programming voltage to program a first cell;
• performing a verify operation on the first cell;
• and
• incrementing the programming voltage by a step voltage if the verify operation determines the first cell is erased wherein the step voltage increases for a predetermined subset of word lines, less than the plurality of word lines, between the lowest word line and the highest word line.

A method for programming a non-volatile memory array having a plurality of memory cells arranged in columns and rows, each column coupled to a different bit line of a plurality of bit lines arranged in odd and even pages and each row coupled by a different word line of a plurality of word lines, a lowest word line being closest to an array source line and a highest word line being closest to an array drain line, the method comprising:

• biasing a first word line with a programming voltage to program a first cell;
• performing a verify operation on the first cell;
• and
• incrementing the programming voltage by a step voltage if the verify operation determines that the first cell is erased wherein the step voltage increases for a predetermined subset of word lines, less than the plurality of word lines, between the lowest word line and the highest word line and wherein the step voltage increase is greater for odd pages of the predetermined subset than for even pages.

A method for programming a non-volatile memory array having a plurality of memory cells arranged in columns and rows, each column coupled to a different bit line of a plurality of bit lines arranged in odd and even pages and each row coupled by a different word line of a plurality of word lines, a lowest word line being closest to an array source line and a highest word line being closest to an array drain line, the method comprising:

• biasing a first word line with a programming voltage to program a first cell;
• performing a verify operation on the first cell;
• and
• incrementing the programming voltage by a step voltage if the verify operation determines that the first cell is erased wherein the step voltage is decreased from a first step voltage associated with the highest word line for a predetermined subset of word lines, less than the plurality of word lines, between the highest word line and the lowest word line and wherein the step voltage decrease is greater for even pages of the predetermined subset than for odd pages.

A memory system comprising:

• a processor that generates memory signals;
• and
• a non-volatile memory device coupled to the processor and operating in response to the memory signals, the device comprising:
• a memory array comprising a plurality of cells organized in rows and columns wherein each row of cells is coupled to a different word line, the array having a source side word line closest to a source line and a drain side word line closest to a drain line;
• and
• control circuitry coupled to the memory array and adapted to control operation of the memory device, the control circuitry adapted to program the memory array by incrementing an initial programming voltage by a step voltage in response to a program verify operation, wherein the step voltage is different for the source side word line than for the drain side word line.

A memory module comprising:

• at least two memory devices, each comprising:
• a memory array comprising a plurality of cells organized in rows and columns wherein each row of cells is coupled to a different word line, the array having a source side word line closest to a source line and a drain side word line closest to a drain line;
• and
• control circuitry coupled to the memory array and adapted to control operation of the memory device, the control circuitry adapted to program the memory array by incrementing an initial programming voltage by a step voltage in response to a program verify operation, wherein the step voltage is different for the source side word line than for the drain side word line;
• and
• a plurality of contacts configured to provide selective contact between the memory device and a host system.

A memory module comprising:

• a memory device comprising:
• a memory array comprising a plurality of cells organized in rows and columns wherein each row of cells is coupled to a different word line, the array having a source side word line closest to a source line and a drain side word line closest to a drain line;
• and
• control circuitry coupled to the memory array and adapted to control operation of the memory device, the control circuitry adapted to program the memory array by incrementing an initial programming voltage by a step voltage in response to a program verify operation, wherein the step voltage is different for the source side word line than for the drain side word line;
• a housing for enclosing the memory device;
• and
• a plurality of contacts coupled to the housing and configured to provide selective contact between the memory device and a host system.